diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 39 |
1 files changed, 25 insertions, 14 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 759df16e6d3..71c1ac7ffbc 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -476,7 +476,7 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI, = MF->getMachineMemOperand(PInfo, MMO->getFlags(), EltSize, MinAlign(Align, EltSize * i)); - BuildMI(*MBB, MI, DL, Desc) + auto MIB = BuildMI(*MBB, MI, DL, Desc) .addReg(SubReg, getDefRegState(!IsStore)) .addReg(ScratchRsrcReg) .addReg(SOffset, SOffsetRegState) @@ -484,8 +484,10 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI, .addImm(0) // glc .addImm(0) // slc .addImm(0) // tfe - .addMemOperand(NewMMO) - .addReg(ValueReg, RegState::Implicit | SrcDstRegState); + .addMemOperand(NewMMO); + + if (NumSubRegs > 1) + MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState); } if (RanOutOfSGPRs) { @@ -689,12 +691,15 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI, .addReg(MFI->getScratchWaveOffsetReg()); } - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR), SubReg) + auto MIB = + BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR), SubReg) .addReg(MFI->getScratchRSrcReg()) // sbase .addReg(OffsetReg) // soff .addImm(0) // glc - .addMemOperand(MMO) - .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); + .addMemOperand(MMO); + + if (NumSubRegs > 1) + MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); continue; } @@ -703,12 +708,14 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI, = MFI->getSpilledReg(MF, Index, i); if (Spill.hasReg()) { - BuildMI(*MBB, MI, DL, - TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), - SubReg) + auto MIB = + BuildMI(*MBB, MI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32), + SubReg) .addReg(Spill.VGPR) - .addImm(Spill.Lane) - .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); + .addImm(Spill.Lane); + + if (NumSubRegs > 1) + MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); } else { // Restore SGPR from a stack slot. // FIXME: We should use S_LOAD_DWORD here for VI. @@ -728,9 +735,13 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI, .addReg(MFI->getScratchWaveOffsetReg()) // soffset .addImm(i * 4) // offset .addMemOperand(MMO); - BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg) - .addReg(TmpReg, RegState::Kill) - .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); + + auto MIB = + BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg) + .addReg(TmpReg, RegState::Kill); + + if (NumSubRegs > 1) + MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); } } |
