diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/pr26625.ll | 20 |
2 files changed, 21 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index a7a5a129f81..4076c7e1ec1 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -6005,7 +6005,7 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _, def : Pat<(_.EltVT (OpNode (load addr:$src))), (!cast<Instruction>(NAME#SUFF#Zm) - (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[OptForSize]>; + (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512, OptForSize]>; } multiclass avx512_sqrt_scalar_all<bits<8> opc, string OpcodeStr> { diff --git a/llvm/test/CodeGen/X86/pr26625.ll b/llvm/test/CodeGen/X86/pr26625.ll new file mode 100644 index 00000000000..1b2e227bb59 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr26625.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -mcpu=i686 2>&1 | FileCheck %s +; PR26625 + +target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128" +target triple = "i386" + +define float @x0(float %f) #0 { +entry: + %call = tail call float @sqrtf(float %f) #1 + ret float %call +; CHECK-LABEL: x0: +; CHECK: flds +; CHECK-NEXT: fsqrt +; CHECK-NOT: vsqrtss +} + +declare float @sqrtf(float) #0 + +attributes #0 = { nounwind optsize readnone } +attributes #1 = { nounwind optsize readnone } |
