diff options
| -rw-r--r-- | clang/include/clang/Basic/arm_mve.td | 33 | ||||
| -rw-r--r-- | clang/include/clang/Basic/arm_mve_defs.td | 7 | ||||
| -rw-r--r-- | clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c | 1638 | ||||
| -rw-r--r-- | llvm/include/llvm/IR/IntrinsicsARM.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrMVE.td | 61 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-var.ll | 1338 |
6 files changed, 3070 insertions, 14 deletions
diff --git a/clang/include/clang/Basic/arm_mve.td b/clang/include/clang/Basic/arm_mve.td index fdc7878c617..87091a32507 100644 --- a/clang/include/clang/Basic/arm_mve.td +++ b/clang/include/clang/Basic/arm_mve.td @@ -688,6 +688,39 @@ let params = T.Int, pnt = PNT_NType in { defm vsri : DyadicImmShift<Vector, imm_1toN>; } +multiclass VSHL_non_imm<string scalarSuffix, int q, int r, + PolymorphicNameType pnt_scalar_unpred = PNT_Type> { + let pnt = pnt_scalar_unpred in { + def scalarSuffix: Intrinsic< + Vector, (args Vector:$in, s32:$sh), + (IRInt<"vshl_scalar", [Vector]> $in, $sh, + q, r, (unsignedflag Scalar))>; + } + def "_m" # scalarSuffix: Intrinsic< + Vector, (args Vector:$in, s32:$sh, Predicate:$pred), + (IRInt<"vshl_scalar_predicated", [Vector, Predicate]> $in, $sh, + q, r, (unsignedflag Scalar), $pred)>; + + def "": Intrinsic< + Vector, (args Vector:$in, SVector:$sh), + (IRInt<"vshl_vector", [Vector, SVector]> $in, $sh, + q, r, (unsignedflag Scalar))>; + defm "": IntrinsicMX< + Vector, (args Vector:$in, SVector:$sh, Predicate:$pred), + (IRInt<"vshl_vector_predicated", [Vector, SVector, Predicate]> $in, $sh, + q, r, (unsignedflag Scalar), $pred, $inactive), + // The saturating shift intrinsics don't have an x variant, so we + // set wantXVariant to 1 iff q == 0 + !eq(q, 0)>; +} + +let params = T.Int in { + defm vshlq : VSHL_non_imm<"_r", 0, 0>; + defm vqshlq : VSHL_non_imm<"_r", 1, 0>; + defm vrshlq : VSHL_non_imm<"_n", 0, 1, PNT_NType>; + defm vqrshlq : VSHL_non_imm<"_n", 1, 1, PNT_NType>; +} + // Base class for the scalar shift intrinsics. class ScalarShift<Type argtype, dag shiftCountArg, dag shiftCodeGen>: Intrinsic<argtype, !con((args argtype:$value), shiftCountArg), shiftCodeGen> { diff --git a/clang/include/clang/Basic/arm_mve_defs.td b/clang/include/clang/Basic/arm_mve_defs.td index 2bd769c220d..a9afddb5796 100644 --- a/clang/include/clang/Basic/arm_mve_defs.td +++ b/clang/include/clang/Basic/arm_mve_defs.td @@ -276,13 +276,16 @@ class HalfSize<Type k> : ComplexType<(CTO_ScaleSize<1, 2> k)>; // Unsigned<t> expects t to be a scalar type, and expands to the unsigned // integer scalar of the same size. So it returns u16 if you give it s16 or -// f16 (or u16 itself). +// f16 (or u16 itself). Similarly, Signed<t> makes the type signed. class Unsigned<Type t>: ComplexType<(CTO_CopyKind t, u32)>; +class Signed<Type t>: ComplexType<(CTO_CopyKind t, s32)>; // UScalar and UVector expand to the unsigned-integer versions of -// Scalar and Vector. +// Scalar and Vector. SScalar and SVector are signed-integer versions. def UScalar: Unsigned<Scalar>; def UVector: VecOf<UScalar>; +def SScalar: Signed<Scalar>; +def SVector: VecOf<SScalar>; // DblVector expands to a vector of scalars of size twice the size of Scalar. // HalfVector, similarly, expands to a vector of half-sized scalars. And diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c new file mode 100644 index 00000000000..680c2e48fb8 --- /dev/null +++ b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-var.c @@ -0,0 +1,1638 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s + +#include <arm_mve.h> + +// CHECK-LABEL: @test_vshlq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vshlq_s8(int8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vshlq(a, b); +#else /* POLYMORPHIC */ + return vshlq_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vshlq_s16(int16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vshlq(a, b); +#else /* POLYMORPHIC */ + return vshlq_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vshlq_s32(int32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vshlq(a, b); +#else /* POLYMORPHIC */ + return vshlq_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vshlq_u8(uint8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vshlq(a, b); +#else /* POLYMORPHIC */ + return vshlq_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vshlq_u16(uint16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vshlq(a, b); +#else /* POLYMORPHIC */ + return vshlq_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vshlq_u32(uint32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vshlq(a, b); +#else /* POLYMORPHIC */ + return vshlq_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_r_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vshlq_r_s8(int8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vshlq_r(a, b); +#else /* POLYMORPHIC */ + return vshlq_r_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_r_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vshlq_r_s16(int16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vshlq_r(a, b); +#else /* POLYMORPHIC */ + return vshlq_r_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_r_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vshlq_r_s32(int32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vshlq_r(a, b); +#else /* POLYMORPHIC */ + return vshlq_r_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_r_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vshlq_r_u8(uint8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vshlq_r(a, b); +#else /* POLYMORPHIC */ + return vshlq_r_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_r_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vshlq_r_u16(uint16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vshlq_r(a, b); +#else /* POLYMORPHIC */ + return vshlq_r_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_r_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vshlq_r_u32(uint32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vshlq_r(a, b); +#else /* POLYMORPHIC */ + return vshlq_r_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vqshlq_s8(int8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vqshlq(a, b); +#else /* POLYMORPHIC */ + return vqshlq_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vqshlq_s16(int16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vqshlq(a, b); +#else /* POLYMORPHIC */ + return vqshlq_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vqshlq_s32(int32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vqshlq(a, b); +#else /* POLYMORPHIC */ + return vqshlq_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vqshlq_u8(uint8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vqshlq(a, b); +#else /* POLYMORPHIC */ + return vqshlq_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vqshlq_u16(uint16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vqshlq(a, b); +#else /* POLYMORPHIC */ + return vqshlq_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vqshlq_u32(uint32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vqshlq(a, b); +#else /* POLYMORPHIC */ + return vqshlq_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_r_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vqshlq_r_s8(int8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqshlq_r(a, b); +#else /* POLYMORPHIC */ + return vqshlq_r_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_r_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vqshlq_r_s16(int16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqshlq_r(a, b); +#else /* POLYMORPHIC */ + return vqshlq_r_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_r_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vqshlq_r_s32(int32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqshlq_r(a, b); +#else /* POLYMORPHIC */ + return vqshlq_r_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_r_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vqshlq_r_u8(uint8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqshlq_r(a, b); +#else /* POLYMORPHIC */ + return vqshlq_r_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_r_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vqshlq_r_u16(uint16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqshlq_r(a, b); +#else /* POLYMORPHIC */ + return vqshlq_r_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_r_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vqshlq_r_u32(uint32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqshlq_r(a, b); +#else /* POLYMORPHIC */ + return vqshlq_r_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vrshlq_s8(int8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vrshlq_s16(int16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vrshlq_s32(int32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vrshlq_u8(uint8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vrshlq_u16(uint16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vrshlq_u32(uint32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_n_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vrshlq_n_s8(int8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_n_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_n_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vrshlq_n_s16(int16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_n_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_n_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vrshlq_n_s32(int32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_n_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_n_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vrshlq_n_u8(uint8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_n_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_n_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vrshlq_n_u16(uint16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_n_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_n_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vrshlq_n_u32(uint32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vrshlq(a, b); +#else /* POLYMORPHIC */ + return vrshlq_n_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vqrshlq_s8(int8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vqrshlq_s16(int16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vqrshlq_s32(int32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vqrshlq_u8(uint8x16_t a, int8x16_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vqrshlq_u16(uint16x8_t a, int16x8_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vqrshlq_u32(uint32x4_t a, int32x4_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_n_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 0) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vqrshlq_n_s8(int8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_n_s8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_n_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 0) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vqrshlq_n_s16(int16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_n_s16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_n_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 0) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vqrshlq_n_s32(int32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_n_s32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_n_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 1) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vqrshlq_n_u8(uint8x16_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_n_u8(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_n_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 1) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vqrshlq_n_u16(uint16x8_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_n_u16(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_n_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 1) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vqrshlq_n_u32(uint32x4_t a, int32_t b) +{ +#ifdef POLYMORPHIC + return vqrshlq(a, b); +#else /* POLYMORPHIC */ + return vqrshlq_n_u32(a, b); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vshlq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_s8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vshlq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_s16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vshlq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_s32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vshlq_m_u8(uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_u8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vshlq_m_u16(uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_u16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vshlq_m_u32(uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_u32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_x_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 0, <16 x i1> [[TMP1]], <16 x i8> undef) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vshlq_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_x_s8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_x_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 0, <8 x i1> [[TMP1]], <8 x i16> undef) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vshlq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_x_s16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_x_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 0, <4 x i1> [[TMP1]], <4 x i32> undef) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vshlq_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_x_s32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_x_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, i32 1, <16 x i1> [[TMP1]], <16 x i8> undef) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vshlq_x_u8(uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_x_u8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_x_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, i32 1, <8 x i1> [[TMP1]], <8 x i16> undef) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vshlq_x_u16(uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_x_u16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_x_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 0, i32 1, <4 x i1> [[TMP1]], <4 x i32> undef) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vshlq_x_u32(uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_x_u32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_r_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 0, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vshlq_m_r_s8(int8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_r_s8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_r_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 0, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vshlq_m_r_s16(int16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_r_s16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_r_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 0, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vshlq_m_r_s32(int32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_r_s32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_r_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 1, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vshlq_m_r_u8(uint8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_r_u8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_r_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 1, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vshlq_m_r_u16(uint16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_r_u16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vshlq_m_r_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 0, i32 1, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vshlq_m_r_u32(uint32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vshlq_m_r_u32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vqshlq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_s8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vqshlq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_s16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vqshlq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_s32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vqshlq_m_u8(uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_u8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vqshlq_m_u16(uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_u16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 0, i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vqshlq_m_u32(uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_u32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_r_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 0, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vqshlq_m_r_s8(int8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_r_s8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_r_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 0, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vqshlq_m_r_s16(int16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_r_s16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_r_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 0, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vqshlq_m_r_s32(int32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_r_s32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_r_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 1, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vqshlq_m_r_u8(uint8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_r_u8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_r_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 1, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vqshlq_m_r_u16(uint16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_r_u16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqshlq_m_r_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 0, i32 1, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vqshlq_m_r_u32(uint32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqshlq_m_r(a, b, p); +#else /* POLYMORPHIC */ + return vqshlq_m_r_u32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vrshlq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_s8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vrshlq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_s16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vrshlq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_s32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vrshlq_m_u8(uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_u8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vrshlq_m_u16(uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_u16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vrshlq_m_u32(uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_u32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_x_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 0, <16 x i1> [[TMP1]], <16 x i8> undef) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vrshlq_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_x_s8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_x_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 0, <8 x i1> [[TMP1]], <8 x i16> undef) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vrshlq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_x_s16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_x_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 0, <4 x i1> [[TMP1]], <4 x i32> undef) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vrshlq_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_x_s32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_x_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, i32 1, <16 x i1> [[TMP1]], <16 x i8> undef) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vrshlq_x_u8(uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_x_u8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_x_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, i32 1, <8 x i1> [[TMP1]], <8 x i16> undef) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vrshlq_x_u16(uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_x_u16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_x_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, i32 1, i32 1, <4 x i1> [[TMP1]], <4 x i32> undef) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vrshlq_x_u32(uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_x(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_x_u32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_n_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 0, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vrshlq_m_n_s8(int8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_n_s8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_n_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 0, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vrshlq_m_n_s16(int16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_n_s16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_n_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 0, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vrshlq_m_n_s32(int32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_n_s32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_n_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 1, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vrshlq_m_n_u8(uint8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_n_u8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_n_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 1, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vrshlq_m_n_u16(uint16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_n_u16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vrshlq_m_n_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i32 1, i32 1, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vrshlq_m_n_u32(uint32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vrshlq_m_n_u32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vqrshlq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_s8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vqrshlq_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_s16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vqrshlq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_s32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vqrshlq_m_u8(uint8x16_t inactive, uint8x16_t a, int8x16_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_u8(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vqrshlq_m_u16(uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_u16(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vqrshlq_m_u32(uint32x4_t inactive, uint32x4_t a, int32x4_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m(inactive, a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_u32(inactive, a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_n_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 0, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +int8x16_t test_vqrshlq_m_n_s8(int8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_n_s8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_n_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 0, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +int16x8_t test_vqrshlq_m_n_s16(int16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_n_s16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_n_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 0, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +int32x4_t test_vqrshlq_m_n_s32(int32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_n_s32(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_n_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 1, <16 x i1> [[TMP1]]) +// CHECK-NEXT: ret <16 x i8> [[TMP2]] +// +uint8x16_t test_vqrshlq_m_n_u8(uint8x16_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_n_u8(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_n_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 1, <8 x i1> [[TMP1]]) +// CHECK-NEXT: ret <8 x i16> [[TMP2]] +// +uint16x8_t test_vqrshlq_m_n_u16(uint16x8_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_n_u16(a, b, p); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vqrshlq_m_n_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 +// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) +// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 1, i32 1, i32 1, <4 x i1> [[TMP1]]) +// CHECK-NEXT: ret <4 x i32> [[TMP2]] +// +uint32x4_t test_vqrshlq_m_n_u32(uint32x4_t a, int32_t b, mve_pred16_t p) +{ +#ifdef POLYMORPHIC + return vqrshlq_m_n(a, b, p); +#else /* POLYMORPHIC */ + return vqrshlq_m_n_u32(a, b, p); +#endif /* POLYMORPHIC */ +} + diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td index fd263d17816..35d40c67b44 100644 --- a/llvm/include/llvm/IR/IntrinsicsARM.td +++ b/llvm/include/llvm/IR/IntrinsicsARM.td @@ -955,6 +955,13 @@ defm int_arm_mve_vshrn: MVEPredicated< llvm_i32_ty /*unsigned-out*/, llvm_i32_ty /*unsigned-in*/, llvm_i32_ty /*top-half*/]>; +defm int_arm_mve_vshl_scalar: MVEPredicated< + [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, + llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>; +defm int_arm_mve_vshl_vector: MVEPredicatedM< + [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty /*shiftcounts*/, + llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>; + // MVE scalar shifts. class ARM_MVE_qrshift_single<list<LLVMType> value, list<LLVMType> saturate = []> : diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index c98f72b053a..19dadf229e5 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -2727,13 +2727,32 @@ class MVE_shift_by_vec<string iname, string suffix, bit U, let validForTailPredication = 1; } +multiclass MVE_shift_by_vec_p<string iname, MVEVectorVTInfo VTI, bit q, bit r> { + def "" : MVE_shift_by_vec<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, q, r>; + + def : Pat<(VTI.Vec (int_arm_mve_vshl_vector + (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh), + (i32 q), (i32 r), (i32 VTI.Unsigned))), + (VTI.Vec (!cast<Instruction>(NAME) + (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh)))>; + + def : Pat<(VTI.Vec (int_arm_mve_vshl_vector_predicated + (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh), + (i32 q), (i32 r), (i32 VTI.Unsigned), + (VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))), + (VTI.Vec (!cast<Instruction>(NAME) + (VTI.Vec MQPR:$in), (VTI.Vec MQPR:$sh), + ARMVCCThen, (VTI.Pred VCCR:$mask), + (VTI.Vec MQPR:$inactive)))>; +} + multiclass mve_shift_by_vec_multi<string iname, bit bit_4, bit bit_8> { - def s8 : MVE_shift_by_vec<iname, "s8", 0b0, 0b00, bit_4, bit_8>; - def s16 : MVE_shift_by_vec<iname, "s16", 0b0, 0b01, bit_4, bit_8>; - def s32 : MVE_shift_by_vec<iname, "s32", 0b0, 0b10, bit_4, bit_8>; - def u8 : MVE_shift_by_vec<iname, "u8", 0b1, 0b00, bit_4, bit_8>; - def u16 : MVE_shift_by_vec<iname, "u16", 0b1, 0b01, bit_4, bit_8>; - def u32 : MVE_shift_by_vec<iname, "u32", 0b1, 0b10, bit_4, bit_8>; + defm s8 : MVE_shift_by_vec_p<iname, MVE_v16s8, bit_4, bit_8>; + defm s16 : MVE_shift_by_vec_p<iname, MVE_v8s16, bit_4, bit_8>; + defm s32 : MVE_shift_by_vec_p<iname, MVE_v4s32, bit_4, bit_8>; + defm u8 : MVE_shift_by_vec_p<iname, MVE_v16u8, bit_4, bit_8>; + defm u16 : MVE_shift_by_vec_p<iname, MVE_v8u16, bit_4, bit_8>; + defm u32 : MVE_shift_by_vec_p<iname, MVE_v4u32, bit_4, bit_8>; } defm MVE_VSHL_by_vec : mve_shift_by_vec_multi<"vshl", 0b0, 0b0>; @@ -4542,13 +4561,31 @@ class MVE_VxSHL_qr<string iname, string suffix, bit U, bits<2> size, let validForTailPredication = 1; } +multiclass MVE_VxSHL_qr_p<string iname, MVEVectorVTInfo VTI, bit q, bit r> { + def "" : MVE_VxSHL_qr<iname, VTI.Suffix, VTI.Unsigned, VTI.Size, q, r>; + + def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar + (VTI.Vec MQPR:$in), (i32 rGPR:$sh), + (i32 q), (i32 r), (i32 VTI.Unsigned))), + (VTI.Vec (!cast<Instruction>(NAME) + (VTI.Vec MQPR:$in), (i32 rGPR:$sh)))>; + + def : Pat<(VTI.Vec (int_arm_mve_vshl_scalar_predicated + (VTI.Vec MQPR:$in), (i32 rGPR:$sh), + (i32 q), (i32 r), (i32 VTI.Unsigned), + (VTI.Pred VCCR:$mask))), + (VTI.Vec (!cast<Instruction>(NAME) + (VTI.Vec MQPR:$in), (i32 rGPR:$sh), + ARMVCCThen, (VTI.Pred VCCR:$mask)))>; +} + multiclass MVE_VxSHL_qr_types<string iname, bit bit_7, bit bit_17> { - def s8 : MVE_VxSHL_qr<iname, "s8", 0b0, 0b00, bit_7, bit_17>; - def s16 : MVE_VxSHL_qr<iname, "s16", 0b0, 0b01, bit_7, bit_17>; - def s32 : MVE_VxSHL_qr<iname, "s32", 0b0, 0b10, bit_7, bit_17>; - def u8 : MVE_VxSHL_qr<iname, "u8", 0b1, 0b00, bit_7, bit_17>; - def u16 : MVE_VxSHL_qr<iname, "u16", 0b1, 0b01, bit_7, bit_17>; - def u32 : MVE_VxSHL_qr<iname, "u32", 0b1, 0b10, bit_7, bit_17>; + defm s8 : MVE_VxSHL_qr_p<iname, MVE_v16s8, bit_7, bit_17>; + defm s16 : MVE_VxSHL_qr_p<iname, MVE_v8s16, bit_7, bit_17>; + defm s32 : MVE_VxSHL_qr_p<iname, MVE_v4s32, bit_7, bit_17>; + defm u8 : MVE_VxSHL_qr_p<iname, MVE_v16u8, bit_7, bit_17>; + defm u16 : MVE_VxSHL_qr_p<iname, MVE_v8u16, bit_7, bit_17>; + defm u32 : MVE_VxSHL_qr_p<iname, MVE_v4u32, bit_7, bit_17>; } defm MVE_VSHL_qr : MVE_VxSHL_qr_types<"vshl", 0b0, 0b0>; diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-var.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-var.ll new file mode 100644 index 00000000000..5c3651374c2 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-var.ll @@ -0,0 +1,1338 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -verify-machineinstrs -o - %s | FileCheck %s + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_s8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vshlq_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_s16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vshlq_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_s32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vshlq_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.s32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_u8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vshlq_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.u8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_u16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vshlq_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.u16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_u32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vshlq_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.u32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_s8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vshlq_r_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_s16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vshlq_r_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_s32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vshlq_r_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_r_u8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vshlq_r_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_r_u16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vshlq_r_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_r_u32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vshlq_r_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vshl.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_s8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vqshlq_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_s16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vqshlq_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_s32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vqshlq_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.s32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_u8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vqshlq_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.u8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_u16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vqshlq_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.u16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_u32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vqshlq_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.u32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_r_s8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vqshlq_r_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_r_s16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vqshlq_r_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_r_s32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vqshlq_r_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_r_u8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vqshlq_r_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_r_u16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vqshlq_r_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_r_u32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vqshlq_r_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqshl.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_s8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vrshlq_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_s16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vrshlq_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_s32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vrshlq_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.s32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_u8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vrshlq_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.u8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_u16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vrshlq_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.u16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_u32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vrshlq_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.u32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_n_s8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vrshlq_n_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_n_s16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vrshlq_n_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_n_s32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vrshlq_n_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_n_u8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vrshlq_n_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_n_u16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vrshlq_n_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_n_u32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vrshlq_n_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vrshl.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_s8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vqrshlq_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_s16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vqrshlq_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_s32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vqrshlq_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.s32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_u8(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vqrshlq_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.u8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_u16(<8 x i16> %a, <8 x i16> %b) { +; CHECK-LABEL: test_vqrshlq_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.u16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_u32(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: test_vqrshlq_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.u32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_n_s8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vqrshlq_n_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 0) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_n_s16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vqrshlq_n_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 0) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_n_s32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vqrshlq_n_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 0) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_n_u8(<16 x i8> %a, i32 %b) { +; CHECK-LABEL: test_vqrshlq_n_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 1) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_n_u16(<8 x i16> %a, i32 %b) { +; CHECK-LABEL: test_vqrshlq_n_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 1) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_n_u32(<4 x i32> %a, i32 %b) { +; CHECK-LABEL: test_vqrshlq_n_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vqrshl.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = call <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 1) + ret <4 x i32> %0 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_x_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 0, <16 x i1> %1, <16 x i8> undef) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_x_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 0, <8 x i1> %1, <8 x i16> undef) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_x_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_x_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, i32 1, <16 x i1> %1, <16 x i8> undef) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_x_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, i32 1, <8 x i1> %1, <8 x i16> undef) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_x_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_r_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_r_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 0, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_r_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_r_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 0, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_r_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_r_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 0, <4 x i1> %1) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vshlq_m_r_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_r_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 0, i32 1, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vshlq_m_r_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_r_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 0, i32 1, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vshlq_m_r_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vshlq_m_r_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vshlt.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 0, i32 1, <4 x i1> %1) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.s8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 0, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.s16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.s32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.u8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, i32 1, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.u16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.u32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_r_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_r_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 0, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_r_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_r_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 0, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_r_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_r_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 0, <4 x i1> %1) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqshlq_m_r_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_r_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 0, i32 1, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqshlq_m_r_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_r_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 0, i32 1, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqshlq_m_r_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqshlq_m_r_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqshlt.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 0, i32 1, <4 x i1> %1) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_x_s8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_x_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0, <16 x i1> %1, <16 x i8> undef) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_x_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_x_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 0, <4 x i1> %1, <4 x i32> undef) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_x_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u8 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 1, <16 x i1> %1, <16 x i8> undef) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_x_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_x_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u32 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, i32 1, <4 x i1> %1, <4 x i32> undef) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_n_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_n_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 0, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_n_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_n_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 0, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_n_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_n_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 0, <4 x i1> %1) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vrshlq_m_n_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_n_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, i32 1, i32 1, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vrshlq_m_n_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_n_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 0, i32 1, i32 1, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vrshlq_m_n_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vrshlq_m_n_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vrshlt.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 0, i32 1, i32 1, <4 x i1> %1) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.s8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 0, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.s16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.s32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.u8 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, i32 1, <16 x i1> %1, <16 x i8> %inactive) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.u16 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r0 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.u32 q0, q1, q2 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_n_s8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_n_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.s8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 0, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_n_s16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_n_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.s16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 0, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_n_s32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_n_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.s32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 0, <4 x i1> %1) + ret <4 x i32> %2 +} + +define arm_aapcs_vfpcc <16 x i8> @test_vqrshlq_m_n_u8(<16 x i8> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_n_u8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.u8 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) + %2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 1, i32 1, i32 1, <16 x i1> %1) + ret <16 x i8> %2 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vqrshlq_m_n_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_n_u16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.u16 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) + %2 = call <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16> %a, i32 %b, i32 1, i32 1, i32 1, <8 x i1> %1) + ret <8 x i16> %2 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vqrshlq_m_n_u32(<4 x i32> %a, i32 %b, i16 zeroext %p) { +; CHECK-LABEL: test_vqrshlq_m_n_u32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vmsr p0, r1 +; CHECK-NEXT: vpst +; CHECK-NEXT: vqrshlt.u32 q0, r0 +; CHECK-NEXT: bx lr +entry: + %0 = zext i16 %p to i32 + %1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) + %2 = call <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32> %a, i32 %b, i32 1, i32 1, i32 1, <4 x i1> %1) + ret <4 x i32> %2 +} + +declare <16 x i8> @llvm.arm.mve.vshl.vector.v16i8.v16i8(<16 x i8>, <16 x i8>, i32, i32, i32) +declare <8 x i16> @llvm.arm.mve.vshl.vector.v8i16.v8i16(<8 x i16>, <8 x i16>, i32, i32, i32) +declare <4 x i32> @llvm.arm.mve.vshl.vector.v4i32.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32) +declare <16 x i8> @llvm.arm.mve.vshl.scalar.v16i8(<16 x i8>, i32, i32, i32, i32) +declare <8 x i16> @llvm.arm.mve.vshl.scalar.v8i16(<8 x i16>, i32, i32, i32, i32) +declare <4 x i32> @llvm.arm.mve.vshl.scalar.v4i32(<4 x i32>, i32, i32, i32, i32) +declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) +declare <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, i32, i32, <16 x i1>, <16 x i8>) +declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) +declare <8 x i16> @llvm.arm.mve.vshl.vector.predicated.v8i16.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, i32, i32, <8 x i1>, <8 x i16>) +declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) +declare <4 x i32> @llvm.arm.mve.vshl.vector.predicated.v4i32.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32, i32, <4 x i1>, <4 x i32>) +declare <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8>, i32, i32, i32, i32, <16 x i1>) +declare <8 x i16> @llvm.arm.mve.vshl.scalar.predicated.v8i16.v8i1(<8 x i16>, i32, i32, i32, i32, <8 x i1>) +declare <4 x i32> @llvm.arm.mve.vshl.scalar.predicated.v4i32.v4i1(<4 x i32>, i32, i32, i32, i32, <4 x i1>) |
