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-rw-r--r--llvm/lib/CodeGen/MachineBasicBlock.cpp46
-rw-r--r--llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll2
-rw-r--r--llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll2
-rw-r--r--llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll4
-rw-r--r--llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll4
-rw-r--r--llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll6
-rw-r--r--llvm/test/CodeGen/Generic/MachineBranchProb.ll10
-rw-r--r--llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll2
-rw-r--r--llvm/test/CodeGen/X86/2010-05-12-FastAllocKills.ll4
-rw-r--r--llvm/test/CodeGen/X86/MachineBranchProb.ll4
-rw-r--r--llvm/test/CodeGen/X86/stack-protector-weight.ll8
-rw-r--r--llvm/test/CodeGen/X86/switch-edge-weight.ll22
12 files changed, 67 insertions, 47 deletions
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 1ed810bf817..7da604cc176 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -270,6 +270,7 @@ void MachineBasicBlock::print(raw_ostream &OS, const SlotIndexes *Indexes,
const Function &F = MF->getFunction();
const Module *M = F.getParent();
ModuleSlotTracker MST(M);
+ MST.incorporateFunction(F);
print(OS, MST, Indexes, IsStandalone);
}
@@ -286,21 +287,40 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (Indexes)
OS << Indexes->getMBBStartIdx(this) << '\t';
- OS << printMBBReference(*this) << ": ";
-
- const char *Comma = "";
- if (const BasicBlock *LBB = getBasicBlock()) {
- OS << Comma << "derived from LLVM BB ";
- LBB->printAsOperand(OS, /*PrintType=*/false, MST);
- Comma = ", ";
+ OS << "bb." << getNumber();
+ bool HasAttributes = false;
+ if (const auto *BB = getBasicBlock()) {
+ if (BB->hasName()) {
+ OS << "." << BB->getName();
+ } else {
+ HasAttributes = true;
+ OS << " (";
+ int Slot = MST.getLocalSlot(BB);
+ if (Slot == -1)
+ OS << "<ir-block badref>";
+ else
+ OS << (Twine("%ir-block.") + Twine(Slot)).str();
+ }
}
- if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
- if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
- if (Alignment)
- OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
- << " bytes)";
- OS << '\n';
+ if (hasAddressTaken()) {
+ OS << (HasAttributes ? ", " : " (");
+ OS << "address-taken";
+ HasAttributes = true;
+ }
+ if (isEHPad()) {
+ OS << (HasAttributes ? ", " : " (");
+ OS << "landing-pad";
+ HasAttributes = true;
+ }
+ if (getAlignment()) {
+ OS << (HasAttributes ? ", " : " (");
+ OS << "align " << getAlignment();
+ HasAttributes = true;
+ }
+ if (HasAttributes)
+ OS << ")";
+ OS << ":\n";
const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
if (!livein_empty()) {
diff --git a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
index b69f121d10c..7e945fd468d 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
@@ -21,7 +21,7 @@ entry:
; Afer if conversion, we have
; for.body -> for.cond.backedge (100%)
; -> cond.false.i (0%)
-; CHECK: %bb.1: derived from LLVM BB %for.body
+; CHECK: bb.1.for.body:
; CHECK: Successors according to CFG: %bb.2(0x80000000 / 0x80000000 = 100.00%) %bb.4(0x00000001 / 0x80000000 = 0.00%)
for.body:
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1
diff --git a/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll b/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
index 6f6f8bc1834..44cf49278db 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-branch-weight.ll
@@ -18,7 +18,7 @@ bb:
%9 = icmp eq i32 %8, 0
br i1 %9, label %return, label %bb2
-; CHECK: %bb.2: derived from LLVM BB %bb2
+; CHECK: bb.2.bb2:
; CHECK: Successors according to CFG: %bb.4({{[0-9a-fx/= ]+}}50.00%) %bb.3({{[0-9a-fx/= ]+}}50.00%)
bb2:
diff --git a/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
index ccc6ded49f1..b2db237aa00 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll
@@ -30,9 +30,9 @@ declare i8* @bar(i32, i8*, i8*)
; CHECK-NEXT: [[FOOCALL]]:
; CHECK-NEXT: bl _foo
;
-; CHECK-PROB: %bb.0:
+; CHECK-PROB: bb.0{{[0-9a-zA-Z.]*}}:
; CHECK-PROB: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}50.00%) %bb.3({{[0-9a-fx/= ]+}}25.00%) %bb.5({{[0-9a-fx/= ]+}}25.00%)
-; CHECK-PROB: %bb.2:
+; CHECK-PROB: bb.2{{[0-9a-zA-Z.]*}}:
; CHECK-PROB: Successors according to CFG: %bb.3({{[0-9a-fx/= ]+}}50.00%) %bb.5({{[0-9a-fx/= ]+}}50.00%)
define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "no-frame-pointer-elim"="true" {
diff --git a/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll b/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll
index f03906b6bf5..3f728b98914 100644
--- a/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll
+++ b/llvm/test/CodeGen/ARM/tail-merge-branch-weight.ll
@@ -10,8 +10,8 @@
; CHECK: # Machine code for function test0:
; CHECK: Successors according to CFG: %bb.{{[0-9]+}}({{[0-9a-fx/= ]+}}20.00%) %bb.{{[0-9]+}}({{[0-9a-fx/= ]+}}80.00%)
-; CHECK: %bb.{{[0-9]+}}:
-; CHECK: %bb.{{[0-9]+}}:
+; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
+; CHECK: bb.{{[0-9]+}}{{[0-9a-zA-Z.]*}}:
; CHECK: # End machine code for function test0.
define i32 @test0(i32 %n, i32 %m, i32* nocapture %a, i32* nocapture %b) {
diff --git a/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll b/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
index 22caecf05c0..e5b99f0b675 100644
--- a/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
+++ b/llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
@@ -9,7 +9,7 @@
;
; This issue manifests in a CFG that looks something like this:
;
-; %bb.2: derived from LLVM BB %finish
+; %bb.2.finish:
; Predecessors according to CFG: %bb.0 %bb.1
; %0 = PHI %3, <%bb.0>, %5, <%bb.1>
; %7 = LDIRdK 2
@@ -49,10 +49,10 @@ dead:
; basic block containing `select` needs to contain explicit jumps to
; both successors.
-; CHECK: %bb.2: derived from LLVM BB %finish
+; CHECK: %bb.2.finish:
; CHECK: BREQk [[BRANCHED:%bb.[0-9]+]]
; CHECK: RJMPk [[DIRECT:%bb.[0-9]+]]
; CHECK: Successors according to CFG
; CHECK-SAME-DAG: {{.*}}[[BRANCHED]]
; CHECK-SAME-DAG: {{.*}}[[DIRECT]]
-; CHECK: %bb.3: derived from LLVM BB
+; CHECK: %bb.3.dead:
diff --git a/llvm/test/CodeGen/Generic/MachineBranchProb.ll b/llvm/test/CodeGen/Generic/MachineBranchProb.ll
index dc4a52ab711..f0d0996ff81 100644
--- a/llvm/test/CodeGen/Generic/MachineBranchProb.ll
+++ b/llvm/test/CodeGen/Generic/MachineBranchProb.ll
@@ -21,13 +21,13 @@ entry:
i64 5, label %sw.bb1
i64 15, label %sw.bb
], !prof !0
-; CHECK: %bb.0: derived from LLVM BB %entry
+; CHECK: bb.0.entry:
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}92.17%) %bb.4({{[0-9a-fx/= ]+}}7.83%)
-; CHECK: %bb.4: derived from LLVM BB %entry
+; CHECK: bb.4.entry:
; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}75.29%) %bb.5({{[0-9a-fx/= ]+}}24.71%)
-; CHECK: %bb.5: derived from LLVM BB %entry
+; CHECK: bb.5.entry:
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}47.62%) %bb.6({{[0-9a-fx/= ]+}}52.38%)
-; CHECK: %bb.6: derived from LLVM BB %entry
+; CHECK: bb.6.entry:
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}36.36%) %bb.3({{[0-9a-fx/= ]+}}63.64%)
sw.bb:
@@ -70,7 +70,7 @@ return: ret void
; right with weight 20.
;
; CHECK-LABEL: Machine code for function left_leaning_weight_balanced_tree:
-; CHECK: %bb.0: derived from LLVM BB %entry
+; CHECK: bb.0.entry:
; CHECK-NOT: Successors
; CHECK: Successors according to CFG: %bb.8({{[0-9a-fx/= ]+}}39.71%) %bb.9({{[0-9a-fx/= ]+}}60.29%)
}
diff --git a/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll b/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll
index 250a81938bd..dbeb7fea864 100644
--- a/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll
+++ b/llvm/test/CodeGen/Hexagon/ifcvt-edge-weight.ll
@@ -1,7 +1,7 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -hexagon-eif=0 -print-machineinstrs=if-converter %s -o /dev/null 2>&1 | FileCheck %s
; Check that the edge weights are updated correctly after if-conversion.
-; CHECK: %bb.3:
+; CHECK: bb.3.if{{[0-9a-zA-Z.]*}}:
; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}10.00%) %bb.1({{[0-9a-fx/= ]+}}90.00%)
@a = external global i32
@d = external global i32
diff --git a/llvm/test/CodeGen/X86/2010-05-12-FastAllocKills.ll b/llvm/test/CodeGen/X86/2010-05-12-FastAllocKills.ll
index 790ccb3ded3..dda8090c296 100644
--- a/llvm/test/CodeGen/X86/2010-05-12-FastAllocKills.ll
+++ b/llvm/test/CodeGen/X86/2010-05-12-FastAllocKills.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
target triple = "x86_64-apple-darwin"
; This test causes a virtual FP register to be redefined while it is live:
-;%bb.5: derived from LLVM BB %bb10
+;%bb.5.bb10:
; Predecessors according to CFG: %bb.4 %bb.5
; %reg1024 = MOV_Fp8080 %reg1034
; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
@@ -13,7 +13,7 @@ target triple = "x86_64-apple-darwin"
; Successors according to CFG: %bb.5
;
; The X86FP pass needs good kill flags, like on %fp0 representing %reg1034:
-;%bb.5: derived from LLVM BB %bb10
+;%bb.5.bb10:
; Predecessors according to CFG: %bb.4 %bb.5
; %fp0 = LD_Fp80m %stack.3, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
; %fp1 = MOV_Fp8080 killed %fp0
diff --git a/llvm/test/CodeGen/X86/MachineBranchProb.ll b/llvm/test/CodeGen/X86/MachineBranchProb.ll
index e6a56651837..3b738142470 100644
--- a/llvm/test/CodeGen/X86/MachineBranchProb.ll
+++ b/llvm/test/CodeGen/X86/MachineBranchProb.ll
@@ -17,9 +17,9 @@ for.cond2: ; preds = %for.inc, %for.cond
%cmp4 = icmp eq i32 %i.1, %v3
%or.cond = or i1 %tobool, %cmp4
br i1 %or.cond, label %for.inc20, label %for.inc, !prof !0
-; CHECK: %bb.1: derived from LLVM BB %for.cond2
+; CHECK: bb.1.for.cond2:
; CHECK: Successors according to CFG: %bb.3({{[0-9a-fx/= ]+}}1.53%) %bb.4({{[0-9a-fx/= ]+}}98.47%)
-; CHECK: %bb.4: derived from LLVM BB %for.cond2
+; CHECK: bb.4.for.cond2:
; CHECK: Successors according to CFG: %bb.3({{[0-9a-fx/= ]+}}1.55%) %bb.2({{[0-9a-fx/= ]+}}98.45%)
for.inc: ; preds = %for.cond2
diff --git a/llvm/test/CodeGen/X86/stack-protector-weight.ll b/llvm/test/CodeGen/X86/stack-protector-weight.ll
index 329b90e933f..30133e4bb1a 100644
--- a/llvm/test/CodeGen/X86/stack-protector-weight.ll
+++ b/llvm/test/CodeGen/X86/stack-protector-weight.ll
@@ -5,14 +5,14 @@
; DARWIN-SELDAG: # Machine code for function test_branch_weights:
; DARWIN-SELDAG: Successors according to CFG: %bb.[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) %bb.[[FAILURE:[0-9]+]]
-; DARWIN-SELDAG: %bb.[[FAILURE]]:
+; DARWIN-SELDAG: bb.[[FAILURE]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-SELDAG: CALL64pcrel32 &__stack_chk_fail
-; DARWIN-SELDAG: %bb.[[SUCCESS]]:
+; DARWIN-SELDAG: bb.[[SUCCESS]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-IR: # Machine code for function test_branch_weights:
; DARWIN-IR: Successors according to CFG: %bb.[[SUCCESS:[0-9]+]]({{[0-9a-fx/= ]+}}100.00%) %bb.[[FAILURE:[0-9]+]]
-; DARWIN-IR: %bb.[[SUCCESS]]:
-; DARWIN-IR: %bb.[[FAILURE]]:
+; DARWIN-IR: bb.[[SUCCESS]]{{[0-9a-zA-Z_.]+}}:
+; DARWIN-IR: bb.[[FAILURE]]{{[0-9a-zA-Z_.]+}}:
; DARWIN-IR: CALL64pcrel32 @__stack_chk_fail
; MSVC-SELDAG: # Machine code for function test_branch_weights:
diff --git a/llvm/test/CodeGen/X86/switch-edge-weight.ll b/llvm/test/CodeGen/X86/switch-edge-weight.ll
index 516c254223f..ed2ca456df5 100644
--- a/llvm/test/CodeGen/X86/switch-edge-weight.ll
+++ b/llvm/test/CodeGen/X86/switch-edge-weight.ll
@@ -31,22 +31,22 @@ sw.epilog:
; Check if weights are correctly assigned to edges generated from switch
; statement.
;
-; CHECK: %bb.0:
+; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.4: [0, 1133] (65 = 60 + 5)
; %bb.0 to %bb.5: [1134, UINT32_MAX] (25 = 20 + 5)
; CHECK: Successors according to CFG: %bb.4({{[0-9a-fx/= ]+}}72.22%) %bb.5({{[0-9a-fx/= ]+}}27.78%)
;
-; CHECK: %bb.4:
+; CHECK: bb.4{{[0-9a-zA-Z.]*}}:
; %bb.4 to %bb.1: [155, 159] (50)
; %bb.4 to %bb.5: [0, 1133] - [155, 159] (15 = 10 + 5)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}76.92%) %bb.7({{[0-9a-fx/= ]+}}23.08%)
;
-; CHECK: %bb.5:
+; CHECK: bb.5{{[0-9a-zA-Z.]*}}:
; %bb.5 to %bb.1: {1140} (10)
; %bb.5 to %bb.6: [1134, UINT32_MAX] - {1140} (15 = 10 + 5)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}40.00%) %bb.6({{[0-9a-fx/= ]+}}60.00%)
;
-; CHECK: %bb.6:
+; CHECK: bb.6{{[0-9a-zA-Z.]*}}:
; %bb.6 to %bb.1: {1134} (10)
; %bb.6 to %bb.2: [1134, UINT32_MAX] - {1134, 1140} (5)
; CHECK: Successors according to CFG: %bb.1({{[0-9a-fx/= ]+}}66.67%) %bb.2({{[0-9a-fx/= ]+}}33.33%)
@@ -99,12 +99,12 @@ sw.epilog:
; Check if weights are correctly assigned to edges generated from switch
; statement.
;
-; CHECK: %bb.0:
+; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: {0} + [15, UINT32_MAX] (5)
; %bb.0 to %bb.8: [1, 14] (jump table) (65 = 60 + 5)
; CHECK: Successors according to CFG: %bb.6({{[0-9a-fx/= ]+}}7.14%) %bb.8({{[0-9a-fx/= ]+}}92.86%
;
-; CHECK: %bb.8:
+; CHECK: bb.8{{[0-9a-zA-Z.]*}}:
; %bb.8 to %bb.1: {1} (10)
; %bb.8 to %bb.6: [2, 9] (5)
; %bb.8 to %bb.2: {10} (10)
@@ -160,12 +160,12 @@ sw.epilog:
; Check if weights are correctly assigned to edges generated from switch
; statement.
;
-; CHECK: %bb.0:
+; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: [0, 9] + [15, UINT32_MAX] {10}
; %bb.0 to %bb.8: [10, 14] (jump table) (50)
; CHECK: Successors according to CFG: %bb.6({{[0-9a-fx/= ]+}}16.67%) %bb.8({{[0-9a-fx/= ]+}}83.33%)
;
-; CHECK: %bb.8:
+; CHECK: bb.8{{[0-9a-zA-Z.]*}}:
; %bb.8 to %bb.1: {10} (10)
; %bb.8 to %bb.2: {11} (10)
; %bb.8 to %bb.3: {12} (10)
@@ -213,12 +213,12 @@ sw.epilog:
; Check if weights are correctly assigned to edges generated from switch
; statement.
;
-; CHECK: %bb.0:
+; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: [0, 110] + [116, UINT32_MAX] (20)
; %bb.0 to %bb.7: [111, 115] (bit test) (50)
; CHECK: Successors according to CFG: %bb.6({{[0-9a-fx/= ]+}}28.57%) %bb.7({{[0-9a-fx/= ]+}}71.43%)
;
-; CHECK: %bb.7:
+; CHECK: bb.7{{[0-9a-zA-Z.]*}}:
; %bb.7 to %bb.2: {111, 114, 115} (30)
; %bb.7 to %bb.3: {112, 113} (20)
; CHECK: Successors according to CFG: %bb.2({{[0-9a-fx/= ]+}}60.00%) %bb.3({{[0-9a-fx/= ]+}}40.00%)
@@ -270,7 +270,7 @@ sw.epilog:
; Check if weights are correctly assigned to edges generated from switch
; statement.
;
-; CHECK: %bb.0:
+; CHECK: bb.0{{[0-9a-zA-Z.]*}}:
; %bb.0 to %bb.6: [10, UINT32_MAX] (15)
; %bb.0 to %bb.8: [4, 20, 28, 36] (jump table) (45)
; CHECK: Successors according to CFG: %bb.8({{[0-9a-fx/= ]+}}25.00%) %bb.9({{[0-9a-fx/= ]+}}75.00%)
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