diff options
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/div1.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll index 89055aa1280..b0865e649d9 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll @@ -22,7 +22,7 @@ define void @divs() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @sj, align 4 @@ -44,7 +44,7 @@ define void @divu() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @uj, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll index cf709e7e495..a5cc24361e6 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll @@ -22,7 +22,7 @@ define void @rems() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @sj, align 4 @@ -45,7 +45,7 @@ define void @remu() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @uj, align 4 |
