diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/vcnt.ll | 62 |
2 files changed, 72 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 13a233d4ecd..3e2eb804727 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -583,6 +583,16 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); setOperationAction(ISD::CTLZ, MVT::v2i64, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i8, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i16, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i32, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v1i64, Expand); + + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand); + // NEON does not have single instruction CTTZ for vectors. setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); setOperationAction(ISD::CTTZ, MVT::v4i16, Custom); diff --git a/llvm/test/CodeGen/ARM/vcnt.ll b/llvm/test/CodeGen/ARM/vcnt.ll index cf0e535f5f3..6d9667bda6f 100644 --- a/llvm/test/CodeGen/ARM/vcnt.ll +++ b/llvm/test/CodeGen/ARM/vcnt.ll @@ -82,6 +82,68 @@ define <2 x i64> @vclzQ64(<2 x i64>* %A) nounwind { ret <2 x i64> %tmp2 } +define <8 x i8> @vclz8b(<8 x i8>* %A) nounwind { +;CHECK-LABEL: vclz8b: +;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}} + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vclz16b(<4 x i16>* %A) nounwind { +;CHECK-LABEL: vclz16b: +;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}} + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vclz32b(<2 x i32>* %A) nounwind { +;CHECK-LABEL: vclz32b: +;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}} + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 1) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vclz64b(<1 x i64>* %A) nounwind { +;CHECK-LABEL: vclz64b: + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %tmp1, i1 1) + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vclzQ8b(<16 x i8>* %A) nounwind { +;CHECK-LABEL: vclzQ8b: +;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 1) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vclzQ16b(<8 x i16>* %A) nounwind { +;CHECK-LABEL: vclzQ16b: +;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}} + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vclzQ32b(<4 x i32>* %A) nounwind { +;CHECK-LABEL: vclzQ32b: +;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}} + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 1) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vclzQ64b(<2 x i64>* %A) nounwind { +;CHECK-LABEL: vclzQ64b: + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %tmp1, i1 1) + ret <2 x i64> %tmp2 +} + declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone |
