diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir | 51 |
2 files changed, 57 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index db8bfc9aac9..716f79e7b75 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -56,6 +56,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::ANDWrr; case TargetOpcode::G_ADD: return AArch64::ADDWrr; + case TargetOpcode::G_SUB: + return AArch64::SUBWrr; default: return GenericOpc; } @@ -67,6 +69,8 @@ static unsigned selectBinaryOp(unsigned GenericOpc, unsigned RegBankID, return AArch64::ANDXrr; case TargetOpcode::G_ADD: return AArch64::ADDXrr; + case TargetOpcode::G_SUB: + return AArch64::SUBXrr; default: return GenericOpc; } @@ -110,7 +114,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { switch (I.getOpcode()) { case TargetOpcode::G_OR: case TargetOpcode::G_AND: - case TargetOpcode::G_ADD: { + case TargetOpcode::G_ADD: + case TargetOpcode::G_SUB: { DEBUG(dbgs() << "AArch64: Selecting: binop\n"); // Reject the various things we don't support yet. diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir index e279ada5797..2924b543fe2 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir @@ -11,6 +11,9 @@ define void @add_s32_gpr() { ret void } define void @add_s64_gpr() { ret void } + define void @sub_s32_gpr() { ret void } + define void @sub_s64_gpr() { ret void } + define void @or_s32_gpr() { ret void } define void @or_s64_gpr() { ret void } @@ -69,6 +72,54 @@ body: | ... --- +# Same as add_s32_gpr, for G_SUB operations. +# CHECK-LABEL: name: sub_s32_gpr +name: sub_s32_gpr +isSSA: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32 } +# CHECK-NEXT: - { id: 1, class: gpr32 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %w0 +# CHECK: %1 = SUBWrr %0, %0 +body: | + bb.0: + liveins: %w0 + + %0(32) = COPY %w0 + %1(32) = G_SUB s32 %0, %0 +... + +--- +# Same as add_s64_gpr, for G_SUB operations. +# CHECK-LABEL: name: sub_s64_gpr +name: sub_s64_gpr +isSSA: true + +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr64 } +# CHECK-NEXT: - { id: 1, class: gpr64 } +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + +# CHECK: body: +# CHECK: %0 = COPY %x0 +# CHECK: %1 = SUBXrr %0, %0 +body: | + bb.0: + liveins: %x0 + + %0(64) = COPY %x0 + %1(64) = G_SUB s64 %0, %0 +... + +--- # Same as add_s32_gpr, for G_OR operations. # CHECK-LABEL: name: or_s32_gpr name: or_s32_gpr |
