diff options
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/unpack-half.ll | 26 |
2 files changed, 33 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 4b5cf6de5a5..ee9b3fde711 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -169,9 +169,15 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N, } SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) { + SDValue Op = N->getOperand(0); + if (Op.getValueType().isVector() + && Op.getValueType().getVectorNumElements() == 1) { + assert(!isSimpleLegalType(Op.getValueType())); + Op = GetScalarizedVector(Op); + } EVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BITCAST, SDLoc(N), - NewVT, N->getOperand(0)); + NewVT, Op); } SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) { diff --git a/llvm/test/CodeGen/AMDGPU/unpack-half.ll b/llvm/test/CodeGen/AMDGPU/unpack-half.ll new file mode 100644 index 00000000000..b2133986ba5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/unpack-half.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck %s + +; On gfx6 and gfx7, this test shows a bug in SelectionDAG where scalarizing the +; extension of a vector of f16 generates an illegal node that errors later. + +; CHECK-LABEL: {{^}}main: +; CHECK: v_cvt_f32_f16 + +define amdgpu_gs void @main(i32 inreg %arg) local_unnamed_addr #0 { +.entry: + %tmp = load volatile float, float addrspace(1)* undef + %tmp1 = bitcast float %tmp to i32 + %im0.i = lshr i32 %tmp1, 16 + %tmp2 = insertelement <2 x i32> undef, i32 %im0.i, i32 1 + %tmp3 = trunc <2 x i32> %tmp2 to <2 x i16> + %tmp4 = bitcast <2 x i16> %tmp3 to <2 x half> + %tmp5 = fpext <2 x half> %tmp4 to <2 x float> + %bc = bitcast <2 x float> %tmp5 to <2 x i32> + %tmp6 = extractelement <2 x i32> %bc, i32 1 + store volatile i32 %tmp6, i32 addrspace(1)* undef + ret void +} + +attributes #0 = { nounwind } + |
