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-rw-r--r--clang-tools-extra/clang-doc/Representation.h4
-rw-r--r--llvm/include/llvm/ADT/STLExtras.h14
-rw-r--r--llvm/utils/TableGen/CodeGenDAGPatterns.cpp2
-rw-r--r--llvm/utils/TableGen/CodeGenRegisters.cpp18
-rw-r--r--llvm/utils/TableGen/CodeGenRegisters.h15
-rw-r--r--llvm/utils/TableGen/RegisterInfoEmitter.cpp4
6 files changed, 23 insertions, 34 deletions
diff --git a/clang-tools-extra/clang-doc/Representation.h b/clang-tools-extra/clang-doc/Representation.h
index 5585773331b..676bf18766a 100644
--- a/clang-tools-extra/clang-doc/Representation.h
+++ b/clang-tools-extra/clang-doc/Representation.h
@@ -61,7 +61,7 @@ struct CommentInfo {
return false;
return std::equal(Children.begin(), Children.end(), Other.Children.begin(),
- llvm::deref<llvm::equal>{});
+ llvm::deref<std::equal_to<>>{});
}
// This operator is used to sort a vector of CommentInfos.
@@ -82,7 +82,7 @@ struct CommentInfo {
if (FirstCI == SecondCI) {
return std::lexicographical_compare(
Children.begin(), Children.end(), Other.Children.begin(),
- Other.Children.end(), llvm::deref<llvm::less>());
+ Other.Children.end(), llvm::deref<std::less<>>());
}
return false;
diff --git a/llvm/include/llvm/ADT/STLExtras.h b/llvm/include/llvm/ADT/STLExtras.h
index af037098226..aa4c9e9646e 100644
--- a/llvm/include/llvm/ADT/STLExtras.h
+++ b/llvm/include/llvm/ADT/STLExtras.h
@@ -1389,20 +1389,6 @@ struct pair_hash {
}
};
-/// A functor like C++14's std::less<void> in its absence.
-struct less {
- template <typename A, typename B> bool operator()(A &&a, B &&b) const {
- return std::forward<A>(a) < std::forward<B>(b);
- }
-};
-
-/// A functor like C++14's std::equal<void> in its absence.
-struct equal {
- template <typename A, typename B> bool operator()(A &&a, B &&b) const {
- return std::forward<A>(a) == std::forward<B>(b);
- }
-};
-
/// Binary functor that adapts to any other binary functor after dereferencing
/// operands.
template <typename T> struct deref {
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index c0e38c032e8..c30186008df 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -1393,7 +1393,7 @@ std::string PatternToMatch::getPredicateCheck() const {
if (!P.getCondString().empty())
PredList.push_back(&P);
}
- llvm::sort(PredList, deref<llvm::less>());
+ llvm::sort(PredList, deref<std::less<>>());
std::string Check;
for (unsigned i = 0, e = PredList.size(); i != e; ++i) {
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index 689809a5cf7..e39e0d7bd8e 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -734,8 +734,8 @@ struct TupleExpander : SetTheory::Expander {
//===----------------------------------------------------------------------===//
static void sortAndUniqueRegisters(CodeGenRegister::Vec &M) {
- llvm::sort(M, deref<llvm::less>());
- M.erase(std::unique(M.begin(), M.end(), deref<llvm::equal>()), M.end());
+ llvm::sort(M, deref<std::less<>>());
+ M.erase(std::unique(M.begin(), M.end(), deref<std::equal_to<>>()), M.end());
}
CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
@@ -860,7 +860,7 @@ void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
return std::binary_search(Members.begin(), Members.end(), Reg,
- deref<llvm::less>());
+ deref<std::less<>>());
}
namespace llvm {
@@ -896,7 +896,7 @@ static bool testSubClass(const CodeGenRegisterClass *A,
return A->RSI.isSubClassOf(B->RSI) &&
std::includes(A->getMembers().begin(), A->getMembers().end(),
B->getMembers().begin(), B->getMembers().end(),
- deref<llvm::less>());
+ deref<std::less<>>());
}
/// Sorting predicate for register classes. This provides a topological
@@ -2140,9 +2140,10 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
const CodeGenRegister::Vec &Memb1 = RC1->getMembers();
const CodeGenRegister::Vec &Memb2 = RC2->getMembers();
CodeGenRegister::Vec Intersection;
- std::set_intersection(
- Memb1.begin(), Memb1.end(), Memb2.begin(), Memb2.end(),
- std::inserter(Intersection, Intersection.begin()), deref<llvm::less>());
+ std::set_intersection(Memb1.begin(), Memb1.end(), Memb2.begin(),
+ Memb2.end(),
+ std::inserter(Intersection, Intersection.begin()),
+ deref<std::less<>>());
// Skip disjoint class pairs.
if (Intersection.empty())
@@ -2167,7 +2168,8 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
// Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
typedef std::map<const CodeGenSubRegIndex *, CodeGenRegister::Vec,
- deref<llvm::less>> SubReg2SetMap;
+ deref<std::less<>>>
+ SubReg2SetMap;
// Compute the set of registers supporting each SubRegIndex.
SubReg2SetMap SRSets;
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index f04a90f8fde..6fb3c3abc1a 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -93,7 +93,8 @@ namespace llvm {
// Map of composite subreg indices.
typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
- deref<llvm::less>> CompMap;
+ deref<std::less<>>>
+ CompMap;
// Returns the subreg index that results from composing this with Idx.
// Returns NULL if this and Idx don't compose.
@@ -137,15 +138,14 @@ namespace llvm {
/// list of subregisters they are composed of (if any). Do this recursively.
void computeConcatTransitiveClosure();
+ bool operator<(const CodeGenSubRegIndex &RHS) const {
+ return this->EnumValue < RHS.EnumValue;
+ }
+
private:
CompMap Composed;
};
- inline bool operator<(const CodeGenSubRegIndex &A,
- const CodeGenSubRegIndex &B) {
- return A.EnumValue < B.EnumValue;
- }
-
/// CodeGenRegister - Represents a register definition.
struct CodeGenRegister {
Record *TheDef;
@@ -156,7 +156,8 @@ namespace llvm {
bool Artificial;
// Map SubRegIndex -> Register.
- typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<llvm::less>>
+ typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *,
+ deref<std::less<>>>
SubRegMap;
CodeGenRegister(Record *R, unsigned Enum);
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 1b619072c81..513cd14e0fa 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -888,7 +888,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
// Keep track of sub-register names as well. These are not differentially
// encoded.
typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec;
- SequenceToOffsetTable<SubRegIdxVec, deref<llvm::less>> SubRegIdxSeqs;
+ SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs;
SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());
SequenceToOffsetTable<std::string> RegStrings;
@@ -1315,7 +1315,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
// Compress the sub-reg index lists.
typedef std::vector<const CodeGenSubRegIndex*> IdxList;
SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
- SequenceToOffsetTable<IdxList, deref<llvm::less>> SuperRegIdxSeqs;
+ SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs;
BitVector MaskBV(RegisterClasses.size());
for (const auto &RC : RegisterClasses) {
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