diff options
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir index 0cf78c4387b..0b056e86496 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -13,6 +13,14 @@ entry: ret void } + define void @defaultMapping1Repair() { + entry: + ret void + } + define void @defaultMapping2Repairs() { + entry: + ret void + } ... --- @@ -47,3 +55,48 @@ body: | ; CHECK: %0(32) = G_ADD <2 x i32> %d0 %0(32) = G_ADD <2 x i32> %d0, %d0 ... + +--- +# Check that we repair the assignment for %0. +# Indeed based on the source of the copy it should live +# in FPR, but at the use, it should be GPR. +name: defaultMapping1Repair +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr } +# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 2, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0.entry: + liveins: %s0, %x0 + ; CHECK: %0(32) = COPY %s0 + ; CHECK-NEXT: %2(32) = COPY %0 + ; CHECK-NEXT: %1(32) = G_ADD i32 %2, %x0 + %0(32) = COPY %s0 + %1(32) = G_ADD i32 %0, %x0 +... + +# Check that we repair the assignment for %0 differently for both uses. +name: defaultMapping2Repairs +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr } +# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 3, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0.entry: + liveins: %s0, %x0 + ; CHECK: %0(32) = COPY %s0 + ; CHECK-NEXT: %2(32) = COPY %0 + ; CHECK-NEXT: %3(32) = COPY %0 + ; CHECK-NEXT: %1(32) = G_ADD i32 %2, %3 + %0(32) = COPY %s0 + %1(32) = G_ADD i32 %0, %0 +... |
