diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCBranchSelector.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 19 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 2 |
5 files changed, 23 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp index 657ff6ce633..36f68058f8f 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -52,7 +52,8 @@ static unsigned getNumBytesForInstruction(MachineInstr *MI) { // minor pessimization that saves us from having to worry about // keeping the offsets up to date later when we emit long branch glue. return 8; - case PPC::IMPLICIT_DEF_GPR: // no asm emitted + case PPC::IMPLICIT_DEF_GPRC: // no asm emitted + case PPC::IMPLICIT_DEF_G8RC: // no asm emitted case PPC::IMPLICIT_DEF_F4: // no asm emitted case PPC::IMPLICIT_DEF_F8: // no asm emitted return 0; diff --git a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp index a530b1e32f2..f1c0e07a048 100644 --- a/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -125,7 +125,8 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) { default: MCE.emitWordBE(getBinaryCodeForInstr(*I)); break; - case PPC::IMPLICIT_DEF_GPR: + case PPC::IMPLICIT_DEF_GPRC: + case PPC::IMPLICIT_DEF_G8RC: case PPC::IMPLICIT_DEF_F8: case PPC::IMPLICIT_DEF_F4: case PPC::IMPLICIT_DEF_VRRC: diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index a417a2d544e..5122b5671b6 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -58,6 +58,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) // PowerPC has no SREM/UREM instructions setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::UREM, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::UREM, MVT::i64, Expand); // We don't support sin/cos/sqrt/fmod setOperationAction(ISD::FSIN , MVT::f64, Expand); diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 0f6c69310cb..99294c5a5cc 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -54,6 +54,14 @@ def HI48_64 : SDNodeXForm<imm, [{ //===----------------------------------------------------------------------===// +// Pseudo instructions. +// + +def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; $rD = IMPLICIT_DEF_G8RC", + [(set G8RC:$rD, (undef))]>; + + +//===----------------------------------------------------------------------===// // Fixed point instructions. // @@ -134,7 +142,12 @@ def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm), "addis $rD, $rA, $imm", IntGeneral, [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; - +def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm), + "subfic $rD, $rA, $imm", IntGeneral, + [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; +def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), + "subf $rT, $rA, $rB", IntGeneral, + [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), @@ -326,9 +339,9 @@ def : Pat<(i32 (trunc G8RC:$in)), (OR8To4 G8RC:$in, G8RC:$in)>; // SHL/SRL -def : Pat<(shl G8RC:$in, (i64 imm:$imm)), +def : Pat<(shl G8RC:$in, (i32 imm:$imm)), (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; -def : Pat<(srl G8RC:$in, (i64 imm:$imm)), +def : Pat<(srl G8RC:$in, (i32 imm:$imm)), (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; // Hi and Lo for Darwin Global Addresses. diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 900ca1a613f..4fd4533b2b9 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -252,7 +252,7 @@ def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt), def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS), "UPDATE_VRSAVE $rD, $rS", []>; } -def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", +def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC", [(set GPRC:$rD, (undef))]>; def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8", [(set F8RC:$rD, (undef))]>; |
