diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInsertWaits.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 |
4 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp index 7df43eeb17e..f250782de58 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp @@ -519,7 +519,7 @@ void SIInsertWaits::insertDPPWaitStates(MachineBasicBlock::iterator DPP, continue; if (DPP->readsRegister(Op.getReg(), TRI)) { - TII->insertWaitStates(DPP, WaitStates); + TII->insertWaitStates(*DPP->getParent(), DPP, WaitStates); return; } } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 81ad0a551c8..ef5b3dbf281 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -801,7 +801,8 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB, return TmpReg; } -void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI, +void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, int Count) const { while (Count > 0) { int Arg; @@ -810,7 +811,7 @@ void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI, else Arg = Count - 1; Count -= 8; - BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP)) + BuildMI(MBB, MI, MI->getDebugLoc(), get(AMDGPU::S_NOP)) .addImm(Arg); } } diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 2ed769de390..ad69f43bf30 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -437,7 +437,8 @@ public: void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, unsigned SavReg, unsigned IndexReg) const; - void insertWaitStates(MachineBasicBlock::iterator MI, int Count) const; + void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI, + int Count) const; /// \brief Returns the operand named \p Op. If \p MI does not have an /// operand named \c Op, this function returns nullptr. diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 744d6bd9fdc..29f48cea4fb 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -414,7 +414,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, case AMDGPUSubtarget::SOUTHERN_ISLANDS: // "VALU writes SGPR" -> "SMRD reads that SGPR" needs 4 wait states // ("S_NOP 3") on SI - TII->insertWaitStates(MI, 4); + TII->insertWaitStates(*MBB, MI, 4); break; case AMDGPUSubtarget::SEA_ISLANDS: break; @@ -422,7 +422,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, // "VALU writes SGPR -> VMEM reads that SGPR" needs 5 wait states // ("S_NOP 4") on VI and later. This also applies to VALUs which write // VCC, but we're unlikely to see VMEM use VCC. - TII->insertWaitStates(MI, 5); + TII->insertWaitStates(*MBB, MI, 5); } MI->eraseFromParent(); |
