summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--llvm/include/llvm/Target/Target.td6
-rw-r--r--llvm/include/llvm/Target/TargetRegisterInfo.h4
2 files changed, 5 insertions, 5 deletions
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index d7356293a0f..1ff8db8c2e6 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -209,9 +209,9 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
code AltOrderSelect = [{}];
// Specify allocation priority for register allocators using a greedy
- // heuristic. Classes with high priority are assigned first. It is sometimes
- // beneficial to assign registers to highly constrained classes first.
- // The priority has to be in the range [0,63].
+ // heuristic. Classes with higher priority values are assigned first. This is
+ // useful as it is sometimes beneficial to assign registers to highly
+ // constrained classes first. The value has to be in the range [0,63].
int AllocationPriority = 0;
}
diff --git a/llvm/include/llvm/Target/TargetRegisterInfo.h b/llvm/include/llvm/Target/TargetRegisterInfo.h
index 7752203b98b..121b8a23252 100644
--- a/llvm/include/llvm/Target/TargetRegisterInfo.h
+++ b/llvm/include/llvm/Target/TargetRegisterInfo.h
@@ -46,8 +46,8 @@ public:
const uint32_t *SubClassMask;
const uint16_t *SuperRegIndices;
const unsigned LaneMask;
- /// Classes with high priority should be assigned first by register allocators
- /// with a greedy heuristic. The priority is a value in the range [0,63].
+ /// Classes with a higher priority value are assigned first by register
+ /// allocators using a greedy heuristic. The value is in the range [0,63].
const uint8_t AllocationPriority;
/// Whether the class supports two (or more) disjunct subregister indices.
const bool HasDisjunctSubRegs;
OpenPOWER on IntegriCloud