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-rw-r--r--llvm/lib/CodeGen/MIRParser/MILexer.cpp1
-rw-r--r--llvm/lib/CodeGen/MIRParser/MILexer.h1
-rw-r--r--llvm/lib/CodeGen/MIRParser/MIParser.cpp19
-rw-r--r--llvm/lib/CodeGen/MachineInstr.cpp21
-rw-r--r--llvm/lib/CodeGen/MachineOperand.cpp7
-rw-r--r--llvm/lib/CodeGen/MachinePipeliner.cpp4
-rw-r--r--llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir2
-rw-r--r--llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir24
-rw-r--r--llvm/test/CodeGen/MIR/X86/memory-operands.mir29
9 files changed, 90 insertions, 18 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index 400e0981a16..e3f19f011ce 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -247,6 +247,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("intpred", MIToken::kw_intpred)
.Case("pre-instr-symbol", MIToken::kw_pre_instr_symbol)
.Case("post-instr-symbol", MIToken::kw_post_instr_symbol)
+ .Case("unknown-size", MIToken::kw_unknown_size)
.Default(MIToken::Identifier);
}
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index 94b460e9ac2..d2dc5511b25 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -115,6 +115,7 @@ struct MIToken {
kw_intpred,
kw_pre_instr_symbol,
kw_post_instr_symbol,
+ kw_unknown_size,
// Named metadata keywords
md_tbaa,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 956f6eceb82..7ba75c13084 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -24,6 +24,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
+#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/AsmParser/Parser.h"
#include "llvm/AsmParser/SlotMapping.h"
#include "llvm/CodeGen/MIRPrinter.h"
@@ -2452,7 +2453,7 @@ bool MIParser::parseOptionalAtomicOrdering(AtomicOrdering &Order) {
return false;
}
- return error("expected an atomic scope, ordering or a size integer literal");
+ return error("expected an atomic scope, ordering or a size specification");
}
bool MIParser::parseMachineMemoryOperand(MachineMemOperand *&Dest) {
@@ -2491,11 +2492,17 @@ bool MIParser::parseMachineMemoryOperand(MachineMemOperand *&Dest) {
if (parseOptionalAtomicOrdering(FailureOrder))
return true;
- if (Token.isNot(MIToken::IntegerLiteral))
- return error("expected the size integer literal after memory operation");
+ if (Token.isNot(MIToken::IntegerLiteral) &&
+ Token.isNot(MIToken::kw_unknown_size))
+ return error("expected the size integer literal or 'unknown-size' after "
+ "memory operation");
uint64_t Size;
- if (getUint64(Size))
- return true;
+ if (Token.is(MIToken::IntegerLiteral)) {
+ if (getUint64(Size))
+ return true;
+ } else if (Token.is(MIToken::kw_unknown_size)) {
+ Size = MemoryLocation::UnknownSize;
+ }
lex();
MachinePointerInfo Ptr = MachinePointerInfo();
@@ -2512,7 +2519,7 @@ bool MIParser::parseMachineMemoryOperand(MachineMemOperand *&Dest) {
if (parseMachinePointerInfo(Ptr))
return true;
}
- unsigned BaseAlignment = Size;
+ unsigned BaseAlignment = (Size != MemoryLocation::UnknownSize ? Size : 1);
AAMDNodes AAInfo;
MDNode *Range = nullptr;
while (consumeIfPresent(MIToken::comma)) {
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 9503537dd67..55dbbd37b4d 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1179,10 +1179,13 @@ bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
int64_t OffsetA = MMOa->getOffset();
int64_t OffsetB = MMOb->getOffset();
-
int64_t MinOffset = std::min(OffsetA, OffsetB);
- int64_t WidthA = MMOa->getSize();
- int64_t WidthB = MMOb->getSize();
+
+ uint64_t WidthA = MMOa->getSize();
+ uint64_t WidthB = MMOb->getSize();
+ bool KnownWidthA = WidthA != MemoryLocation::UnknownSize;
+ bool KnownWidthB = WidthB != MemoryLocation::UnknownSize;
+
const Value *ValA = MMOa->getValue();
const Value *ValB = MMOb->getValue();
bool SameVal = (ValA && ValB && (ValA == ValB));
@@ -1198,6 +1201,8 @@ bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
}
if (SameVal) {
+ if (!KnownWidthA || !KnownWidthB)
+ return true;
int64_t MaxOffset = std::max(OffsetA, OffsetB);
int64_t LowWidth = (MinOffset == OffsetA) ? WidthA : WidthB;
return (MinOffset + LowWidth > MaxOffset);
@@ -1212,13 +1217,15 @@ bool MachineInstr::mayAlias(AliasAnalysis *AA, MachineInstr &Other,
assert((OffsetA >= 0) && "Negative MachineMemOperand offset");
assert((OffsetB >= 0) && "Negative MachineMemOperand offset");
- int64_t Overlapa = WidthA + OffsetA - MinOffset;
- int64_t Overlapb = WidthB + OffsetB - MinOffset;
+ int64_t OverlapA = KnownWidthA ? WidthA + OffsetA - MinOffset
+ : MemoryLocation::UnknownSize;
+ int64_t OverlapB = KnownWidthB ? WidthB + OffsetB - MinOffset
+ : MemoryLocation::UnknownSize;
AliasResult AAResult = AA->alias(
- MemoryLocation(ValA, Overlapa,
+ MemoryLocation(ValA, OverlapA,
UseTBAA ? MMOa->getAAInfo() : AAMDNodes()),
- MemoryLocation(ValB, Overlapb,
+ MemoryLocation(ValB, OverlapB,
UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
return (AAResult != NoAlias);
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index 8098333832b..a116d8fe877 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -14,6 +14,7 @@
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Analysis/Loads.h"
+#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/CodeGen/MIRPrinter.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
@@ -1078,7 +1079,11 @@ void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (getFailureOrdering() != AtomicOrdering::NotAtomic)
OS << toIRString(getFailureOrdering()) << ' ';
- OS << getSize();
+ if (getSize() == MemoryLocation::UnknownSize)
+ OS << "unknown-size";
+ else
+ OS << getSize();
+
if (const Value *Val = getValue()) {
OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
printIRValueReference(OS, *Val, MST);
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index 943a2b42200..c8d2c492b98 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -3190,8 +3190,8 @@ void SwingSchedulerDAG::updateMemOperands(MachineInstr &NewMI,
NewMMOs.push_back(
MF.getMachineMemOperand(MMO, AdjOffset, MMO->getSize()));
} else {
- NewMI.dropMemRefs(MF);
- return;
+ NewMMOs.push_back(
+ MF.getMachineMemOperand(MMO, 0, MemoryLocation::UnknownSize));
}
}
NewMI.setMemRefs(MF, NewMMOs);
diff --git a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
index 3666c8499b8..537f25e8b06 100644
--- a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
+++ b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
@@ -17,7 +17,7 @@ liveins:
body: |
bb.0.entry:
liveins: $rdi
- ; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size integer literal
+ ; CHECK: [[@LINE+1]]:53: expected an atomic scope, ordering or a size specification
$eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load from %ir.a)
RETQ $eax
...
diff --git a/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
new file mode 100644
index 00000000000..4a80455425d
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
@@ -0,0 +1,24 @@
+# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+ define i32 @test(i32* %a) {
+ entry:
+ %b = load i32, i32* %a
+ ret i32 %b
+ }
+
+...
+---
+name: test
+tracksRegLiveness: true
+liveins:
+ - { reg: '$rdi' }
+body: |
+ bb.0.entry:
+ liveins: $rdi
+ ; CHECK: [[@LINE+1]]:53: expected the size integer literal or 'unknown-size' after memory operation
+ $eax = MOV32rm killed $rdi, 1, _, 0, _ :: (load . from %ir.a)
+ RETQ $eax
+...
+
diff --git a/llvm/test/CodeGen/MIR/X86/memory-operands.mir b/llvm/test/CodeGen/MIR/X86/memory-operands.mir
index 85e31c09d1c..2ac7bea2fc9 100644
--- a/llvm/test/CodeGen/MIR/X86/memory-operands.mir
+++ b/llvm/test/CodeGen/MIR/X86/memory-operands.mir
@@ -189,6 +189,8 @@
define void @dummy0() { ret void }
define void @dummy1() { ret void }
+ define void @dummy2() { ret void }
+ define void @dummy3() { ret void }
...
---
name: test
@@ -532,5 +534,30 @@ body: |
bb.0:
$rax = MOV64rm $rsp, 1, _, 0, _ :: (load 8 from %stack.0)
RETQ $rax
-
+...
+---
+# Test parsing of unknown size in machine memory operands without alignment.
+# CHECK-LABEL: name: dummy2
+# CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load unknown-size from %stack.0, align 1)
+name: dummy2
+tracksRegLiveness: true
+stack:
+ - { id: 0, size: 4, alignment: 4 }
+body: |
+ bb.0:
+ $rax = MOV64rm $rsp, 1, _, 0, _ :: (load unknown-size from %stack.0)
+ RETQ $rax
+...
+---
+# Test parsing of unknown size in machine memory operands with alignment.
+# CHECK-LABEL: name: dummy3
+# CHECK: $rax = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load unknown-size from %stack.0, align 4)
+name: dummy3
+tracksRegLiveness: true
+stack:
+ - { id: 0, size: 4, alignment: 4 }
+body: |
+ bb.0:
+ $rax = MOV64rm $rsp, 1, _, 0, _ :: (load unknown-size from %stack.0, align 4)
+ RETQ $rax
...
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