diff options
25 files changed, 208 insertions, 52 deletions
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 26b5c4360d9..9dff4f131db 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -31,6 +31,9 @@ #include "llvm/IR/GlobalVariable.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "mips-fastisel" using namespace llvm; @@ -95,6 +98,7 @@ class MipsFastISel final : public FastISel { // Convenience variables to avoid some queries. LLVMContext *Context; + bool fastLowerArguments() override; bool fastLowerCall(CallLoweringInfo &CLI) override; bool fastLowerIntrinsicCall(const IntrinsicInst *II) override; @@ -195,6 +199,9 @@ private: bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs, unsigned &NumBytes); bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes); + const MipsABIInfo &getABI() const { + return static_cast<const MipsTargetMachine &>(TM).getABI(); + } public: // Backend specific FastISel code. @@ -208,8 +215,7 @@ public: bool ISASupported = !Subtarget->hasMips32r6() && !Subtarget->inMicroMipsMode() && Subtarget->hasMips32(); TargetSupported = - ISASupported && TM.isPositionIndependent() && - (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32()); + ISASupported && TM.isPositionIndependent() && getABI().IsO32(); UnsupportedFPMode = Subtarget->isFP64bit(); } @@ -1249,6 +1255,156 @@ bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, return true; } +bool MipsFastISel::fastLowerArguments() { + DEBUG(dbgs() << "fastLowerArguments\n"); + + if (!FuncInfo.CanLowerReturn) { + DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n"); + return false; + } + + const Function *F = FuncInfo.Fn; + if (F->isVarArg()) { + DEBUG(dbgs() << ".. gave up (varargs)\n"); + return false; + } + + CallingConv::ID CC = F->getCallingConv(); + if (CC != CallingConv::C) { + DEBUG(dbgs() << ".. gave up (calling convention is not C)\n"); + return false; + } + + static const MCPhysReg GPR32ArgRegs[] = {Mips::A0, Mips::A1, Mips::A2, + Mips::A3}; + static const MCPhysReg FGR32ArgRegs[] = {Mips::F12, Mips::F14}; + static const MCPhysReg AFGR64ArgRegs[] = {Mips::D6, Mips::D7}; + + struct AllocatedReg { + const TargetRegisterClass *RC; + unsigned Reg; + AllocatedReg(const TargetRegisterClass *RC, unsigned Reg) + : RC(RC), Reg(Reg) {} + }; + + // Only handle simple cases. i.e. Up to four integer arguments. + // Supporting floating point significantly complicates things so we leave + // that out for now. + SmallVector<AllocatedReg, 4> Allocation; + unsigned Idx = 1; + bool HasAllocatedNonFGR = false; + for (const auto &FormalArg : F->args()) { + if (Idx > 4) { + DEBUG(dbgs() << ".. gave up (too many arguments)\n"); + return false; + } + + if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) || + F->getAttributes().hasAttribute(Idx, Attribute::StructRet) || + F->getAttributes().hasAttribute(Idx, Attribute::ByVal)) { + DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n"); + return false; + } + + Type *ArgTy = FormalArg.getType(); + if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) { + DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n"); + return false; + } + + EVT ArgVT = TLI.getValueType(DL, ArgTy); + DEBUG(dbgs() << ".. " << (Idx - 1) << ": " << ArgVT.getEVTString() << "\n"); + if (!ArgVT.isSimple()) { + DEBUG(dbgs() << ".. .. gave up (not a simple type)\n"); + return false; + } + + switch (ArgVT.getSimpleVT().SimpleTy) { + case MVT::i1: + case MVT::i8: + case MVT::i16: + if (!F->getAttributes().hasAttribute(Idx, Attribute::SExt) && + !F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) { + // It must be any extend, this shouldn't happen for clang-generated IR + // so just fall back on SelectionDAG. + DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n"); + return false; + } + DEBUG(dbgs() << ".. .. GPR32(" << GPR32ArgRegs[Idx - 1] << ")\n"); + Allocation.emplace_back(&Mips::GPR32RegClass, GPR32ArgRegs[Idx - 1]); + HasAllocatedNonFGR = true; + break; + + case MVT::i32: + if (F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) { + // The O32 ABI does not permit a zero-extended i32. + DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n"); + return false; + } + DEBUG(dbgs() << ".. .. GPR32(" << GPR32ArgRegs[Idx - 1] << ")\n"); + Allocation.emplace_back(&Mips::GPR32RegClass, GPR32ArgRegs[Idx - 1]); + HasAllocatedNonFGR = true; + break; + + case MVT::f32: + if (Idx > 2 || HasAllocatedNonFGR) { + DEBUG(dbgs() << ".. .. gave up (f32 arg needed i32)\n"); + return false; + } else { + DEBUG(dbgs() << ".. .. FGR32(" << FGR32ArgRegs[Idx - 1] << ")\n"); + Allocation.emplace_back(&Mips::FGR32RegClass, FGR32ArgRegs[Idx - 1]); + } + break; + + case MVT::f64: + if (Idx > 2 || HasAllocatedNonFGR) { + DEBUG(dbgs() << ".. .. gave up (f64 arg needed 2xi32)\n"); + return false; + } else { + DEBUG(dbgs() << ".. .. AFGR64(" << AFGR64ArgRegs[Idx - 1] << ")\n"); + Allocation.emplace_back(&Mips::AFGR64RegClass, AFGR64ArgRegs[Idx - 1]); + } + break; + + default: + DEBUG(dbgs() << ".. .. gave up (unknown type)\n"); + return false; + } + + ++Idx; + } + + Idx = 0; + for (const auto &FormalArg : F->args()) { + unsigned SrcReg = Allocation[Idx].Reg; + unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[Idx].RC); + // FIXME: Unfortunately it's necessary to emit a copy from the livein copy. + // Without this, EmitLiveInCopies may eliminate the livein if its only + // use is a bitcast (which isn't turned into an instruction). + unsigned ResultReg = createResultReg(Allocation[Idx].RC); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + TII.get(TargetOpcode::COPY), ResultReg) + .addReg(DstReg, getKillRegState(true)); + updateValueMap(&FormalArg, ResultReg); + ++Idx; + } + + // Calculate the size of the incoming arguments area. + // We currently reject all the cases where this would be non-zero. + unsigned IncomingArgSizeInBytes = 0; + + // Account for the reserved argument area on ABI's that have one (O32). + // It seems strange to do this on the caller side but it's necessary in + // SelectionDAG's implementation. + IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC), + IncomingArgSizeInBytes); + + MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes, + false); + + return true; +} + bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) { if (!TargetSupported) return false; diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll index a448e90187c..2f2a3304270 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @b = global i32 1, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll index 8f1f703ea07..bdbc41ce569 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/bswap1.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=3 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=3 | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @a = global i16 -21829, align 2 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll b/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll index 9988622db54..417ee2cd96f 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \ +; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,32R1 ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \ +; RUN: -fast-isel-abort=3 -verify-machineinstrs < %s | \ ; RUN: FileCheck %s -check-prefixes=ALL,32R2 declare void @xb(i8) diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll b/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll index d6d9074c7c1..f27791a9241 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/constexpr-address.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic \ -; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s +; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s ; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic \ -; RUN: -fast-isel=true -fast-isel-abort=1 < %s | FileCheck %s +; RUN: -fast-isel=true -fast-isel-abort=3 < %s | FileCheck %s @ARR = external global [10 x i32], align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll index b0865e649d9..f565af258f2 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/div1.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=3 | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=3 | FileCheck %s @sj = global i32 200000, align 4 @sk = global i32 -47, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll index 9c91567eabf..c420a044578 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s -verify-machineinstrs | FileCheck %s %struct.x = type { i32 } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll index d661a281ea1..b27b20c8f71 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s @f1 = common global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll index f78289f40a0..d9637af9263 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpext.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @f = global float 0x40147E6B80000000, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll index 2c022be5b3f..9a9570f21b3 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fpintconv.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll index 89a7bfce5b0..61828737aab 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/fptrunc.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @d = global double 0x40147E6B74DF0446, align 8 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll index fc37e118e75..cc19beafd38 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @c = global i32 4, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll index 46f7a42a5fe..dc7be744ddc 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll @@ -4,9 +4,9 @@ target triple = "mips--linux-gnu" @c2 = common global i8 0, align 1 @c1 = common global i8 0, align 1 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @s2 = common global i16 0, align 2 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll index 09b56d2c87e..7e52fb40842 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @b2 = global i8 0, align 1 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll index 1051b2800e5..78077f7642f 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll index fec85092fff..0519c07682e 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s @ub1 = common global i8 0, align 1 @ub2 = common global i8 0, align 1 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll index 7deb5c08ec6..aca6aa569ba 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \ +; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \ +; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll index 106015e30c3..617b9bb07dd 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/nullvoid.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll index 37e87b29c58..ed1dc215735 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @x = common global [128000 x float] zeroinitializer, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll index a5cc24361e6..c8524a5b81e 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/rem1.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=3 | FileCheck %s ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s +; RUN: -fast-isel-abort=3 | FileCheck %s @sj = global i32 200, align 4 @sk = global i32 -47, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll index 20747c4ed20..d8d1222d3e3 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/retabi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s @i = global i32 75, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll index bbea9c5566c..184db73ceab 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 \ -; RUN: -fast-isel-abort=1 -mcpu=mips32r2 < %s | FileCheck %s +; RUN: -fast-isel-abort=3 -mcpu=mips32r2 < %s | FileCheck %s ; RUN: llc -march=mipsel -relocation-model=pic -O0 \ -; RUN: -fast-isel-abort=1 -mcpu=mips32 < %s | FileCheck %s +; RUN: -fast-isel-abort=3 -mcpu=mips32 < %s | FileCheck %s @s1 = global i16 -89, align 2 @s2 = global i16 4, align 2 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll index 627a383f597..1379390039a 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @abcd = external global i32 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll index 62101d8ef7e..4ee60bf5e61 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32r2 -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s -check-prefix=mips32 @f = common global float 0.000000e+00, align 4 diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll index 67541b54bae..c4a8e55425b 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \ ; RUN: < %s | FileCheck %s -; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ +; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32 \ ; RUN: < %s | FileCheck %s @ijk = external global i32 |
