diff options
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/SystemZ/SystemZISelLowering.h | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/DAGCombine_trunc_extract.ll | 18 |
3 files changed, 24 insertions, 2 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 7f0cb11dc35..140ee29e5f1 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -4736,8 +4736,11 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { } // Return true if VT is a vector whose elements are a whole number of bytes -// in width. -static bool canTreatAsByteVector(EVT VT) { +// in width. Also check for presence of vector support. +bool SystemZTargetLowering::canTreatAsByteVector(EVT VT) const { + if (!Subtarget.hasVector()) + return false; + return VT.isVector() && VT.getScalarSizeInBits() % 8 == 0 && VT.isSimple(); } diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h index 7a21a474c11..7d92a735587 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -537,6 +537,7 @@ private: unsigned UnpackHigh) const; SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const; + bool canTreatAsByteVector(EVT VT) const; SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp, unsigned Index, DAGCombinerInfo &DCI, bool Force) const; diff --git a/llvm/test/CodeGen/SystemZ/DAGCombine_trunc_extract.ll b/llvm/test/CodeGen/SystemZ/DAGCombine_trunc_extract.ll new file mode 100644 index 00000000000..63c1c636318 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/DAGCombine_trunc_extract.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=s390x-linux-gnu -mcpu=zEC12 < %s | FileCheck %s +; +; Check that DAGCombiner doesn't crash in SystemZ combineTruncateExtract() +; when handling EXTRACT_VECTOR_ELT without vector support. + +define void @autogen_SD21598(<2 x i8> %Arg) { +; CHECK: stc %r3, 0(%r1) +; CHECK: j .LBB0_1 + +entry: + br label %loop + +loop: ; preds = %CF249, %CF247 + %Shuff = shufflevector <2 x i8> undef, <2 x i8> %Arg, <2 x i32> <i32 3, i32 1> + %E = extractelement <2 x i8> %Shuff, i32 0 + store i8 %E, i8* undef + br label %loop +} |
