diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/README.txt | 18 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/lbz-from-ld-shift.ll | 18 |
2 files changed, 18 insertions, 18 deletions
diff --git a/llvm/lib/Target/PowerPC/README.txt b/llvm/lib/Target/PowerPC/README.txt index f705139e680..9565ae131f8 100644 --- a/llvm/lib/Target/PowerPC/README.txt +++ b/llvm/lib/Target/PowerPC/README.txt @@ -255,24 +255,6 @@ int f(signed char *a, _Bool b, _Bool c) { ===-------------------------------------------------------------------------=== -This: -int test(unsigned *P) { return *P >> 24; } - -Should compile to: - -_test: - lbz r3,0(r3) - blr - -not: - -_test: - lwz r2, 0(r3) - srwi r3, r2, 24 - blr - -===-------------------------------------------------------------------------=== - On the G5, logical CR operations are more expensive in their three address form: ops that read/write the same register are half as expensive as those that read from two registers that are different from their destination. diff --git a/llvm/test/CodeGen/PowerPC/lbz-from-ld-shift.ll b/llvm/test/CodeGen/PowerPC/lbz-from-ld-shift.ll new file mode 100644 index 00000000000..3eacd6a45fb --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/lbz-from-ld-shift.ll @@ -0,0 +1,18 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readonly +define signext i32 @test(i32* nocapture readonly %P) #0 { +entry: + %0 = load i32* %P, align 4 + %shr = lshr i32 %0, 24 + ret i32 %shr + +; CHECK-LABEL: @test +; CHECK: lbz 3, 0(3) +; CHECK: blr +} + +attributes #0 = { nounwind readonly } + |
