diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 2 |
2 files changed, 5 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp index 5ed7fdf220b..6f332fd5b33 100644 --- a/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp +++ b/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp @@ -218,7 +218,7 @@ FunctionPass *llvm::createSIPeepholeSDWAPass() { #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) -static raw_ostream& operator<<(raw_ostream &OS, const SdwaSel &Sel) { +static raw_ostream& operator<<(raw_ostream &OS, SdwaSel Sel) { switch(Sel) { case BYTE_0: OS << "BYTE_0"; break; case BYTE_1: OS << "BYTE_1"; break; @@ -984,7 +984,7 @@ bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, } } - // Apply all sdwa operand pattenrs + // Apply all sdwa operand patterns. bool Converted = false; for (auto &Operand : SDWAOperands) { // There should be no intesection between SDWA operands and potential MIs @@ -1017,7 +1017,8 @@ bool SIPeepholeSDWA::convertToSDWA(MachineInstr &MI, // If an instruction was converted to SDWA it should not have immediates or SGPR // operands (allowed one SGPR on GFX9). Copy its scalar operands into VGPRs. -void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI, const SISubtarget &ST) const { +void SIPeepholeSDWA::legalizeScalarOperands(MachineInstr &MI, + const SISubtarget &ST) const { const MCInstrDesc &Desc = TII->get(MI.getOpcode()); unsigned ConstantBusCount = 0; for (MachineOperand &Op : MI.explicit_uses()) { diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll index de5229e0550..47e6545d0a0 100644 --- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll +++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll @@ -498,7 +498,7 @@ entry: ret void } -; GCN-LABEL: {{^}}sdwa_crash_inlineasm_de +; GCN-LABEL: {{^}}sdwa_crash_inlineasm_def: ; GCN: s_mov_b32 s{{[0-9]+}}, 0xffff ; GCN: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_or_b32_e32 v{{[0-9]+}}, 0x10000, |
