diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonPatternsHVX.td | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonPseudo.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll | 41 |
4 files changed, 58 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 0a38783388b..66e38cfc8b9 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1153,6 +1153,14 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { MBB.erase(MI); return true; } + case Hexagon::PS_vdd0: { + unsigned Vd = MI.getOperand(0).getReg(); + BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) + .addReg(Vd, RegState::Undef) + .addReg(Vd, RegState::Undef); + MBB.erase(MI); + return true; + } case Hexagon::PS_vmulw: { // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies. unsigned DstReg = MI.getOperand(0).getReg(); diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td index 3b075cacf5e..16242905bcd 100644 --- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td +++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td @@ -185,10 +185,13 @@ let Predicates = [UseHVX] in { def: Pat<(VecI8 vzero), (V6_vd0)>; def: Pat<(VecI16 vzero), (V6_vd0)>; def: Pat<(VecI32 vzero), (V6_vd0)>; - // Use V6_vsubw_dv instead. - def: Pat<(VecPI8 vzero), (Combinev (V6_vd0), (V6_vd0))>; - def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>; - def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>; + def: Pat<(VecPI8 vzero), (PS_vdd0)>; + def: Pat<(VecPI16 vzero), (PS_vdd0)>; + def: Pat<(VecPI32 vzero), (PS_vdd0)>; + + def: Pat<(concat_vectors (VecI8 vzero), (VecI8 vzero)), (PS_vdd0)>; + def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>; + def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>; def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)), (Combinev HvxVR:$Vt, HvxVR:$Vs)>; diff --git a/llvm/lib/Target/Hexagon/HexagonPseudo.td b/llvm/lib/Target/Hexagon/HexagonPseudo.td index 0a8907de4e8..ede27c11485 100644 --- a/llvm/lib/Target/Hexagon/HexagonPseudo.td +++ b/llvm/lib/Target/Hexagon/HexagonPseudo.td @@ -461,6 +461,8 @@ let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1, V6_veqw.Itinerary, TypeCVI_VA>; def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "", V6_vgtw.Itinerary, TypeCVI_VA>; + def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "", + V6_vsubw_dv.Itinerary, TypeCVI_VA_DV>; } // Store predicate. diff --git a/llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll b/llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll new file mode 100644 index 00000000000..7bf17b952c7 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/autohvx/vdd0.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; CHECK-LABEL: f0: +; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) +define <128 x i8> @f0() #0 { + ret <128 x i8> zeroinitializer +} + +; CHECK-LABEL: f1: +; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) +define <64 x i16> @f1() #0 { + ret <64 x i16> zeroinitializer +} + +; CHECK-LABEL: f2: +; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) +define <32 x i32> @f2() #0 { + ret <32 x i32> zeroinitializer +} + +; CHECK-LABEL: f3: +; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) +define <256 x i8> @f3() #1 { + ret <256 x i8> zeroinitializer +} + +; CHECK-LABEL: f4: +; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) +define <128 x i16> @f4() #1 { + ret <128 x i16> zeroinitializer +} + +; CHECK-LABEL: f5: +; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w) +define <64 x i32> @f5() #1 { + ret <64 x i32> zeroinitializer +} + +attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } +attributes #1 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } + |
