diff options
| -rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/Verifier/test_g_add.mir | 28 | ||||
| -rw-r--r-- | llvm/test/Verifier/test_g_trunc.mir | 23 |
3 files changed, 59 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index cc8f77e823d..b7e0f575406 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -940,9 +940,12 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { if (isFunctionSelected) report("Unexpected generic instruction in a Selected function", MI); + unsigned NumOps = MI->getNumOperands(); + // Check types. SmallVector<LLT, 4> Types; - for (unsigned I = 0; I < MCID.getNumOperands(); ++I) { + for (unsigned I = 0, E = std::min(MCID.getNumOperands(), NumOps); + I != E; ++I) { if (!MCID.OpInfo[I].isGenericType()) continue; // Generic instructions specify type equality constraints between some of @@ -973,6 +976,10 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { if (MO->isReg() && TargetRegisterInfo::isPhysicalRegister(MO->getReg())) report("Generic instruction cannot have physical register", MO, I); } + + // Avoid out of bounds in checks below. This was already reported earlier. + if (MI->getNumOperands() < MCID.getNumOperands()) + return; } StringRef ErrorInfo; @@ -1033,8 +1040,6 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { // instructions aren't guaranteed to have the right number of operands or // types attached to them at this point assert(MCID.getNumOperands() == 2 && "Expected 2 operands G_*{EXT,TRUNC}"); - if (MI->getNumOperands() < MCID.getNumOperands()) - break; LLT DstTy = MRI->getType(MI->getOperand(0).getReg()); LLT SrcTy = MRI->getType(MI->getOperand(1).getReg()); if (!DstTy.isValid() || !SrcTy.isValid()) diff --git a/llvm/test/Verifier/test_g_add.mir b/llvm/test/Verifier/test_g_add.mir new file mode 100644 index 00000000000..54c470adc8a --- /dev/null +++ b/llvm/test/Verifier/test_g_add.mir @@ -0,0 +1,28 @@ +#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# REQUIRES: global-isel, aarch64-registered-target + +--- +name: test_add +legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +liveins: +body: | + bb.0: + + %0:_(s32) = G_CONSTANT i32 0 + %1:_(s32) = G_CONSTANT i32 1 + + ; CHECK: Bad machine code: Too few operands + %2:_(s32) = G_ADD + + ; CHECK: Bad machine code: Too few operands + %3:_(s32) = G_ADD %0 + %4:_(s32) = G_ADD %0, %1 + + ; CHECK: Bad machine code: Too few operands + ; CHECK: Bad machine code: Explicit definition marked as use + G_ADD %0, %1 + +... diff --git a/llvm/test/Verifier/test_g_trunc.mir b/llvm/test/Verifier/test_g_trunc.mir new file mode 100644 index 00000000000..3a196bb7bbd --- /dev/null +++ b/llvm/test/Verifier/test_g_trunc.mir @@ -0,0 +1,23 @@ +# RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# REQUIRES: global-isel, aarch64-registered-target + +--- +name: test_trunc +legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +liveins: +body: | + bb.0: + + ; CHECK: Bad machine code: Too few operands + %0:_(s32) = G_TRUNC + + %1:_(s64) = G_IMPLICIT_DEF + + ; CHECK: Bad machine code: Too few operands + ; CHECK: Bad machine code: Explicit definition marked as use + G_TRUNC %1 + +... |
