diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/vld1.ll | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/vst1.ll | 10 |
3 files changed, 21 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 69415792aac..9621743fe30 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -1784,6 +1784,7 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, case MVT::v8i16: OpcodeIndex = 1; break; case MVT::v4f32: case MVT::v4i32: OpcodeIndex = 2; break; + case MVT::v2f64: case MVT::v2i64: OpcodeIndex = 3; assert(NumVecs == 1 && "v2i64 type only supported for VLD1"); break; @@ -1920,6 +1921,7 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, case MVT::v8i16: OpcodeIndex = 1; break; case MVT::v4f32: case MVT::v4i32: OpcodeIndex = 2; break; + case MVT::v2f64: case MVT::v2i64: OpcodeIndex = 3; assert(NumVecs == 1 && "v2i64 type only supported for VST1"); break; diff --git a/llvm/test/CodeGen/ARM/vld1.ll b/llvm/test/CodeGen/ARM/vld1.ll index caeeada90ff..db640f54b0e 100644 --- a/llvm/test/CodeGen/ARM/vld1.ll +++ b/llvm/test/CodeGen/ARM/vld1.ll @@ -119,6 +119,14 @@ define <2 x i64> @vld1Qi64(i64* %A) nounwind { ret <2 x i64> %tmp1 } +define <2 x double> @vld1Qf64(double* %A) nounwind { +;CHECK-LABEL: vld1Qf64: +;CHECK: vld1.64 + %tmp0 = bitcast double* %A to i8* + %tmp1 = call <2 x double> @llvm.arm.neon.vld1.v2f64(i8* %tmp0, i32 1) + ret <2 x double> %tmp1 +} + declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*, i32) nounwind readonly declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*, i32) nounwind readonly declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly @@ -130,6 +138,7 @@ declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly +declare <2 x double> @llvm.arm.neon.vld1.v2f64(i8*, i32) nounwind readonly ; Radar 8355607 ; Do not crash if the vld1 result is not used. diff --git a/llvm/test/CodeGen/ARM/vst1.ll b/llvm/test/CodeGen/ARM/vst1.ll index 14f3ff06630..a6bcf7d8ead 100644 --- a/llvm/test/CodeGen/ARM/vst1.ll +++ b/llvm/test/CodeGen/ARM/vst1.ll @@ -117,6 +117,15 @@ define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind { ret void } +define void @vst1Qf64(double* %A, <2 x double>* %B) nounwind { +;CHECK-LABEL: vst1Qf64: +;CHECK: vst1.64 + %tmp0 = bitcast double* %A to i8* + %tmp1 = load <2 x double>* %B + call void @llvm.arm.neon.vst1.v2f64(i8* %tmp0, <2 x double> %tmp1, i32 1) + ret void +} + declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind @@ -128,3 +137,4 @@ declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>, i32) nounwind +declare void @llvm.arm.neon.vst1.v2f64(i8*, <2 x double>, i32) nounwind |
