diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 11 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/fast-isel-int-ext5.ll | 19 |
2 files changed, 25 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 99cb641340b..3ead55c40a9 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -1917,7 +1917,8 @@ bool AArch64FastISel::selectLoad(const Instruction *I) { // could select it. Emit a copy to subreg if necessary. FastISel will remove // it when it selects the integer extend. unsigned Reg = lookUpRegForValue(IntExtVal); - if (!Reg) { + auto *MI = MRI.getUniqueVRegDef(Reg); + if (!MI) { if (RetVT == MVT::i64 && VT <= MVT::i32) { if (WantZExt) { // Delete the last emitted instruction from emitLoad (SUBREG_TO_REG). @@ -1935,10 +1936,7 @@ bool AArch64FastISel::selectLoad(const Instruction *I) { // The integer extend has already been emitted - delete all the instructions // that have been emitted by the integer extend lowering code and use the // result from the load instruction directly. - while (Reg) { - auto *MI = MRI.getUniqueVRegDef(Reg); - if (!MI) - break; + while (MI) { Reg = 0; for (auto &Opnd : MI->uses()) { if (Opnd.isReg()) { @@ -1947,6 +1945,9 @@ bool AArch64FastISel::selectLoad(const Instruction *I) { } } MI->eraseFromParent(); + MI = nullptr; + if (Reg) + MI = MRI.getUniqueVRegDef(Reg); } updateValueMap(IntExtVal, ResultReg); return true; diff --git a/llvm/test/CodeGen/AArch64/fast-isel-int-ext5.ll b/llvm/test/CodeGen/AArch64/fast-isel-int-ext5.ll new file mode 100644 index 00000000000..0f9ec62811d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/fast-isel-int-ext5.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s + +; CHECK-LABEL: int_ext_opt +define i64 @int_ext_opt(i8* %addr, i1 %c1, i1 %c2) { +entry: + %0 = load i8, i8* %addr + br i1 %c1, label %bb1, label %bb2 + +bb1: + %1 = zext i8 %0 to i64 + br i1 %c2, label %bb2, label %exit + +bb2: + %2 = phi i64 [1, %entry], [%1, %bb1] + ret i64 %2 + +exit: + ret i64 0 +} |
