diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedPredicates.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td index 028ad2232c9..fc13b23b4cf 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td @@ -322,7 +322,7 @@ def IsLoadRegOffsetOp : CheckOpcode<[PRFMroW, PRFMroX, LDRDroW, LDRDroX, LDRQroW, LDRQroX]>; -// Identify whether an instruction is a load +// Identify whether an instruction is a store // using the register offset addressing mode. def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX, STRHHroW, STRHHroX, |
