diff options
| author | David Tellenbach <david.tellenbach@me.com> | 2019-11-23 19:11:31 +0100 |
|---|---|---|
| committer | David Tellenbach <david.tellenbach@me.com> | 2019-11-23 19:11:31 +0100 |
| commit | b8e6319f3ef7f9e87cecefc73326dd025455c019 (patch) | |
| tree | 7dfe8986d2768ca4258587be8cf35d4f98bbd512 | |
| parent | 4736d63f752f8d13f4c6a9afd558565c32119718 (diff) | |
| download | bcm5719-llvm-b8e6319f3ef7f9e87cecefc73326dd025455c019.tar.gz bcm5719-llvm-b8e6319f3ef7f9e87cecefc73326dd025455c019.zip | |
[NFC] [AArch64] Fix wrong documentation for IsStoreRegOffsetOp
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SchedPredicates.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td index 028ad2232c9..fc13b23b4cf 100644 --- a/llvm/lib/Target/AArch64/AArch64SchedPredicates.td +++ b/llvm/lib/Target/AArch64/AArch64SchedPredicates.td @@ -322,7 +322,7 @@ def IsLoadRegOffsetOp : CheckOpcode<[PRFMroW, PRFMroX, LDRDroW, LDRDroX, LDRQroW, LDRQroX]>; -// Identify whether an instruction is a load +// Identify whether an instruction is a store // using the register offset addressing mode. def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX, STRHHroW, STRHHroX, |
