diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 31 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/absimm.ll | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/zextloadi1.ll | 1 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/Hexagon/st.txt | 1 | ||||
| -rw-r--r-- | llvm/test/MC/Hexagon/instructions/st.s | 1 |
6 files changed, 20 insertions, 29 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 618ea316e65..7857cfafac8 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -3320,9 +3320,9 @@ let isCall = 1, Uses = [R29, R31], isAsmParserOnly = 1 in { //===----------------------------------------------------------------------===// let hasSideEffects = 0, isPredicable = 1 in class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp, - bits<2>MajOp, Operand AddrOp, bit isAbs, bit isHalf> - : STInst<(outs), (ins AddrOp:$addr, RC:$src), - mnemonic # !if(isAbs, "(##", "(#")#"$addr) = $src"#!if(isHalf, ".h",""), + bits<2>MajOp, bit isAbs, bit isHalf> + : STInst<(outs), (ins ImmOp:$addr, RC:$src), + mnemonic # "(#$addr) = $src"#!if(isHalf, ".h",""), [], "", V2LDST_tc_st_SLOT01> { bits<19> addr; bits<5> src; @@ -3355,7 +3355,7 @@ class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp, let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp, bit isHalf, bit isNot, bit isNew> - : STInst<(outs), (ins PredRegs:$src1, u6Ext:$absaddr, RC: $src2), + : STInst<(outs), (ins PredRegs:$src1, u32MustExt:$absaddr, RC: $src2), !if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ", ") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""), [], "", ST_tc_st_SLOT01>, AddrModeRel { @@ -3387,7 +3387,7 @@ class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp, //===----------------------------------------------------------------------===// class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp, bits<2> MajOp, bit isHalf> - : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, u32Imm, 1, isHalf>, + : T_StoreAbsGP <mnemonic, RC, u32MustExt, MajOp, 1, isHalf>, AddrModeRel { string ImmOpStr = !cast<string>(ImmOp); let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19, @@ -3554,7 +3554,7 @@ defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>; let isAsmParserOnly = 1 in class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp, bits<2> MajOp, bit isHalf = 0> - : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> { + : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, 0, isHalf> { // Set BaseOpcode same as absolute addressing instructions so that // non-predicated GP-Rel instructions can have relate with predicated // Absolute instruction. @@ -3569,7 +3569,7 @@ multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp, // Absolute instruction. let BaseOpcode = BaseOp#_abs in { def NAME#gp : T_StoreAbsGP <mnemonic, IntRegs, ImmOp, MajOp, - globaladdress, 0, isHalf>; + 0, isHalf>; // New-value store def NAME#newgp : T_StoreAbsGP_NV <mnemonic, ImmOp, MajOp, 0> ; } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index c407e7cb166..9d950b84cc4 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -87,28 +87,23 @@ public: StringRef Contents(Buffer); auto PacketBundle = Contents.rsplit('\n'); auto HeadTail = PacketBundle.first.split('\n'); - auto Preamble = "\t{\n\t\t"; - auto Separator = ""; - while(!HeadTail.first.empty()) { - OS << Separator; - StringRef Inst; + StringRef Separator = "\n"; + StringRef Indent = "\t\t"; + OS << "\t{\n"; + while (!HeadTail.first.empty()) { + StringRef InstTxt; auto Duplex = HeadTail.first.split('\v'); - if(!Duplex.second.empty()){ - OS << Duplex.first << "\n"; - Inst = Duplex.second; + if (!Duplex.second.empty()) { + OS << Indent << Duplex.first << Separator; + InstTxt = Duplex.second; + } else if (!HeadTail.first.trim().startswith("immext")) { + InstTxt = Duplex.first; } - else { - if(!HeadTail.first.startswith("immext")) - Inst = Duplex.first; - } - OS << Preamble; - OS << Inst; + if (!InstTxt.empty()) + OS << Indent << InstTxt << Separator; HeadTail = HeadTail.second.split('\n'); - Preamble = ""; - Separator = "\n\t\t"; } - if(HexagonMCInstrInfo::bundleSize(Inst) != 0) - OS << "\n\t}" << PacketBundle.second; + OS << "\t}" << PacketBundle.second; } }; } diff --git a/llvm/test/CodeGen/Hexagon/absimm.ll b/llvm/test/CodeGen/Hexagon/absimm.ll index f3f10f2b4f2..e67af5e8fef 100644 --- a/llvm/test/CodeGen/Hexagon/absimm.ll +++ b/llvm/test/CodeGen/Hexagon/absimm.ll @@ -1,7 +1,6 @@ ; RUN: llc -march=hexagon < %s | FileCheck %s ; Check that we generate absolute addressing mode instructions ; with immediate value. -; XFAIL: * define i32 @f1(i32 %i) nounwind { ; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/zextloadi1.ll b/llvm/test/CodeGen/Hexagon/zextloadi1.ll index c6c982750c0..9ce7bea9fce 100644 --- a/llvm/test/CodeGen/Hexagon/zextloadi1.ll +++ b/llvm/test/CodeGen/Hexagon/zextloadi1.ll @@ -1,5 +1,4 @@ ; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s -; XFAIL: * ; CHECK: r{{[0-9]+}} = ##i129_l+16 ; CHECK: r{{[0-9]+}} = ##i129_s+16 diff --git a/llvm/test/MC/Disassembler/Hexagon/st.txt b/llvm/test/MC/Disassembler/Hexagon/st.txt index 4da3b54be8b..6d9074a05ef 100644 --- a/llvm/test/MC/Disassembler/Hexagon/st.txt +++ b/llvm/test/MC/Disassembler/Hexagon/st.txt @@ -1,6 +1,5 @@ # RUN: llvm-mc -triple=hexagon -disassemble < %s | FileCheck %s # Hexagon Programmer's Reference Manual 11.8 ST -# XFAIL: * # Store doubleword 0x9e 0xf5 0xd1 0x3b diff --git a/llvm/test/MC/Hexagon/instructions/st.s b/llvm/test/MC/Hexagon/instructions/st.s index 38822a62043..3b5e8ee1810 100644 --- a/llvm/test/MC/Hexagon/instructions/st.s +++ b/llvm/test/MC/Hexagon/instructions/st.s @@ -1,6 +1,5 @@ # RUN: llvm-mc -triple=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s # Hexagon Programmer's Reference Manual 11.8 ST -# XFAIL: * # Store doubleword # CHECK: 9e f5 d1 3b |
