diff options
| -rw-r--r-- | llvm/include/llvm/CodeGen/MachineInstrBuilder.h | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp | 12 | 
2 files changed, 11 insertions, 12 deletions
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h index 917eead97d7..7b0dcc151e0 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h @@ -386,6 +386,17 @@ inline unsigned getDebugRegState(bool B) {    return B ? RegState::Debug : 0;  } +/// Get all register state flags from machine operand \p RegOp. +inline unsigned getRegState(const MachineOperand &RegOp) { +  assert(RegOp.isReg() && "Not a register operand"); +  return getDefRegState(RegOp.isDef())                    | +         getImplRegState(RegOp.isImplicit())              | +         getKillRegState(RegOp.isKill())                  | +         getDeadRegState(RegOp.isDead())                  | +         getUndefRegState(RegOp.isUndef())                | +         getInternalReadRegState(RegOp.isInternalRead())  | +         getDebugRegState(RegOp.isDebug()); +}  /// Helper class for constructing bundles of MachineInstrs.  /// diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp index 62999e5f170..9571778b560 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -108,18 +108,6 @@ INITIALIZE_PASS(HexagonSplitDoubleRegs, "hexagon-split-double",    "Hexagon Split Double Registers", false, false) -static inline uint32_t getRegState(const MachineOperand &R) { -  assert(R.isReg()); -  return getDefRegState(R.isDef()) | -         getImplRegState(R.isImplicit()) | -         getKillRegState(R.isKill()) | -         getDeadRegState(R.isDead()) | -         getUndefRegState(R.isUndef()) | -         getInternalReadRegState(R.isInternalRead()) | -         (R.isDebug() ? RegState::Debug : 0); -} - -  void HexagonSplitDoubleRegs::dump_partition(raw_ostream &os,        const USet &Part, const TargetRegisterInfo &TRI) {    dbgs() << '{';  | 

