diff options
| -rw-r--r-- | clang/lib/CodeGen/CGBuiltin.cpp | 1 | ||||
| -rw-r--r-- | clang/test/CodeGen/palignr.c | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 9e538703177..463b3eee3d3 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -6238,6 +6238,7 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID, // but less than two lanes, convert to shifting in zeroes. if (ShiftVal > NumLaneElts) { ShiftVal -= NumLaneElts; + Ops[1] = Ops[0]; Ops[0] = llvm::Constant::getNullValue(Ops[0]->getType()); } diff --git a/clang/test/CodeGen/palignr.c b/clang/test/CodeGen/palignr.c index 1712df5256c..5a77597c340 100644 --- a/clang/test/CodeGen/palignr.c +++ b/clang/test/CodeGen/palignr.c @@ -4,13 +4,13 @@ #define _mm_alignr_epi8(a, b, n) (__builtin_ia32_palignr128((a), (b), (n))) typedef __attribute__((vector_size(16))) int int4; -// CHECK: palignr +// CHECK: palignr $15, %xmm1, %xmm0 int4 align1(int4 a, int4 b) { return _mm_alignr_epi8(a, b, 15); } // CHECK: ret // CHECK: ret // CHECK-NOT: palignr int4 align2(int4 a, int4 b) { return _mm_alignr_epi8(a, b, 16); } -// CHECK: psrldq +// CHECK: psrldq $1, %xmm0 int4 align3(int4 a, int4 b) { return _mm_alignr_epi8(a, b, 17); } // CHECK: xor int4 align4(int4 a, int4 b) { return _mm_alignr_epi8(a, b, 32); } |
