diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll | 44 |
2 files changed, 18 insertions, 28 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index cff58f37ae1..5f7d22d3b1f 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -5072,7 +5072,7 @@ def VACGThd : N3VDInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt", "f16", v4i16, v4f16, int_arm_neon_vacgt, 0>, Requires<[HasNEON, HasFullFP16]>; def VACGThq : N3VQInt<1, 0, 0b11, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt", - "f16", v8f16, v8f16, int_arm_neon_vacgt, 0>, + "f16", v8i16, v8f16, int_arm_neon_vacgt, 0>, Requires<[HasNEON, HasFullFP16]>; // VTST : Vector Test Bits defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, diff --git a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll index 2b532a82b0e..0141159d187 100644 --- a/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll +++ b/llvm/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll @@ -522,19 +522,23 @@ entry: ret <8 x i16> %vcageq_v2.i } -; FIXME (PR38404) -; -;define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) { -;entry: -; %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b) -; ret <4 x i16> %vcagt_v2.i -;} -; -;define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) { -;entry: -; %vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b) -; ret <8 x i16> %vcagtq_v2.i -;} +define dso_local <4 x i16> @test_vcagt_f16(<4 x half> %a, <4 x half> %b) { +; CHECK-LABEL: test_vcagt_f16: +; CHECK: vacgt.f16 d0, d0, d1 +; CHECK-NEXT: bx lr +entry: + %vcagt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %a, <4 x half> %b) + ret <4 x i16> %vcagt_v2.i +} + +define dso_local <8 x i16> @test_vcagtq_f16(<8 x half> %a, <8 x half> %b) { +; CHECK-LABEL: test_vcagtq_f16: +; CHECK: vacgt.f16 q0, q0, q1 +; CHECK-NEXT: bx lr +entry: + %vcagtq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %a, <8 x half> %b) + ret <8 x i16> %vcagtq_v2.i +} define dso_local <4 x i16> @test_vcale_f16(<4 x half> %a, <4 x half> %b) { ; CHECKLABEL: test_vcale_f16: @@ -554,20 +558,6 @@ entry: ret <8 x i16> %vcaleq_v2.i } -; FIXME (PR38404) -; -;define dso_local <4 x i16> @test_vcalt_f16(<4 x half> %a, <4 x half> %b) { -;entry: -; %vcalt_v2.i = tail call <4 x i16> @llvm.arm.neon.vacgt.v4i16.v4f16(<4 x half> %b, <4 x half> %a) -; ret <4 x i16> %vcalt_v2.i -;} - -;define dso_local <8 x i16> @test_vcaltq_f16(<8 x half> %a, <8 x half> %b) { -;entry: -; %vcaltq_v2.i = tail call <8 x i16> @llvm.arm.neon.vacgt.v8i16.v8f16(<8 x half> %b, <8 x half> %a) -; ret <8 x i16> %vcaltq_v2.i -;} - define dso_local <4 x i16> @test_vceq_f16(<4 x half> %a, <4 x half> %b) { ; CHECKLABEL: test_vceq_f16: ; CHECK: vceq.f16 d0, d0, d1 |
