diff options
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM64/vmul.ll | 7 |
2 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp b/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp index 63957abdfdd..0fcafc1f87e 100644 --- a/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp +++ b/llvm/lib/Target/ARM64/ARM64ISelLowering.cpp @@ -173,6 +173,8 @@ ARM64TargetLowering::ARM64TargetLowering(ARM64TargetMachine &TM) setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); + setOperationAction(ISD::MUL, MVT::v1i64, Expand); + // Custom lowering hooks are needed for XOR // to fold it into CSINC/CSINV. setOperationAction(ISD::XOR, MVT::i32, Custom); diff --git a/llvm/test/CodeGen/ARM64/vmul.ll b/llvm/test/CodeGen/ARM64/vmul.ll index d11bb2f72eb..b6bd16ac0b4 100644 --- a/llvm/test/CodeGen/ARM64/vmul.ll +++ b/llvm/test/CodeGen/ARM64/vmul.ll @@ -2027,3 +2027,10 @@ define <16 x i8> @test_pmull_high_64(<2 x i64> %l, <2 x i64> %r) nounwind { } declare <16 x i8> @llvm.arm64.neon.pmull64(i64, i64) + +define <1 x i64> @test_mul_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) nounwind { +; CHECK-LABEL: test_mul_v1i64: +; CHECK: mul + %prod = mul <1 x i64> %lhs, %rhs + ret <1 x i64> %prod +} |
