diff options
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 44 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 40 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 52 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 46 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/schedule-x86_64.ll | 58 |
6 files changed, 124 insertions, 124 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index e60471409ff..79deb4b65b9 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -1217,8 +1217,8 @@ def: InstRW<[BWWriteResGroup27], (instregex "COMISSrr")>; def: InstRW<[BWWriteResGroup27], (instregex "CVTDQ2PSrr")>; def: InstRW<[BWWriteResGroup27], (instregex "CVTPS2DQrr")>; def: InstRW<[BWWriteResGroup27], (instregex "CVTTPS2DQrr")>; -def: InstRW<[BWWriteResGroup27], (instregex "IMUL(32|64)rr")>; -def: InstRW<[BWWriteResGroup27], (instregex "IMUL8r")>; +def: InstRW<[BWWriteResGroup27], (instrs IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>; +def: InstRW<[BWWriteResGroup27], (instrs IMUL8r)>; def: InstRW<[BWWriteResGroup27], (instregex "LZCNT(16|32|64)rr")>; def: InstRW<[BWWriteResGroup27], (instregex "MAX(C?)PDrr")>; def: InstRW<[BWWriteResGroup27], (instregex "MAX(C?)PSrr")>; @@ -1229,7 +1229,7 @@ def: InstRW<[BWWriteResGroup27], (instregex "MIN(C?)PSrr")>; def: InstRW<[BWWriteResGroup27], (instregex "MIN(C?)SDrr")>; def: InstRW<[BWWriteResGroup27], (instregex "MIN(C?)SSrr")>; def: InstRW<[BWWriteResGroup27], (instregex "MMX_CVTPI2PSirr")>; -def: InstRW<[BWWriteResGroup27], (instregex "MUL8r")>; +def: InstRW<[BWWriteResGroup27], (instrs MUL8r)>; def: InstRW<[BWWriteResGroup27], (instregex "PDEP(32|64)rr")>; def: InstRW<[BWWriteResGroup27], (instregex "PEXT(32|64)rr")>; def: InstRW<[BWWriteResGroup27], (instregex "POPCNT(16|32|64)rr")>; @@ -1298,7 +1298,7 @@ def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[BWWriteResGroup27_16], (instregex "IMUL16rr")>; +def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> { let Latency = 3; @@ -1522,14 +1522,14 @@ def: InstRW<[BWWriteResGroup42], (instregex "CVTSI642SDrr")>; def: InstRW<[BWWriteResGroup42], (instregex "CVTSI2SDrr")>; def: InstRW<[BWWriteResGroup42], (instregex "CVTSI2SSrr")>; def: InstRW<[BWWriteResGroup42], (instregex "CVTTPD2DQrr")>; -def: InstRW<[BWWriteResGroup42], (instregex "IMUL(32|64)r")>; +def: InstRW<[BWWriteResGroup42], (instrs IMUL32r, IMUL64r)>; def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr")>; def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPI2PDirr")>; def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPS2PIirr")>; def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTTPD2PIirr")>; def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTTPS2PIirr")>; -def: InstRW<[BWWriteResGroup42], (instregex "MUL(32|64)r")>; -def: InstRW<[BWWriteResGroup42], (instregex "MULX64rr")>; +def: InstRW<[BWWriteResGroup42], (instrs MUL32r, MUL64r)>; +def: InstRW<[BWWriteResGroup42], (instrs MULX64rr)>; def: InstRW<[BWWriteResGroup42], (instregex "VCVTDQ2PDrr")>; def: InstRW<[BWWriteResGroup42], (instregex "VCVTPD2DQrr")>; def: InstRW<[BWWriteResGroup42], (instregex "VCVTPD2PSrr")>; @@ -1544,8 +1544,8 @@ def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { let Latency = 4; let NumMicroOps = 4; } -def: InstRW<[BWWriteResGroup42_16], (instregex "IMUL16r")>; -def: InstRW<[BWWriteResGroup42_16], (instregex "MUL16r")>; +def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r)>; +def: InstRW<[BWWriteResGroup42_16], (instrs MUL16r)>; def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> { let Latency = 4; @@ -1740,7 +1740,7 @@ def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup52], (instregex "MULX32rr")>; +def: InstRW<[BWWriteResGroup52], (instrs MULX32rr)>; def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> { let Latency = 5; @@ -2576,9 +2576,9 @@ def: InstRW<[BWWriteResGroup91], (instregex "COMISSrm")>; def: InstRW<[BWWriteResGroup91], (instregex "CVTDQ2PSrm")>; def: InstRW<[BWWriteResGroup91], (instregex "CVTPS2DQrm")>; def: InstRW<[BWWriteResGroup91], (instregex "CVTTPS2DQrm")>; -def: InstRW<[BWWriteResGroup91], (instregex "IMUL64m")>; -def: InstRW<[BWWriteResGroup91], (instregex "IMUL(32|64)rm(i8)?")>; -def: InstRW<[BWWriteResGroup91], (instregex "IMUL8m")>; +def: InstRW<[BWWriteResGroup91], (instrs IMUL64m)>; +def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>; +def: InstRW<[BWWriteResGroup91], (instrs IMUL8m)>; def: InstRW<[BWWriteResGroup91], (instregex "LZCNT(16|32|64)rm")>; def: InstRW<[BWWriteResGroup91], (instregex "MAX(C?)PDrm")>; def: InstRW<[BWWriteResGroup91], (instregex "MAX(C?)PSrm")>; @@ -2591,8 +2591,8 @@ def: InstRW<[BWWriteResGroup91], (instregex "MIN(C?)SSrm")>; def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm")>; def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPS2PIirm")>; def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTTPS2PIirm")>; -def: InstRW<[BWWriteResGroup91], (instregex "MUL64m")>; -def: InstRW<[BWWriteResGroup91], (instregex "MUL8m")>; +def: InstRW<[BWWriteResGroup91], (instrs MUL64m)>; +def: InstRW<[BWWriteResGroup91], (instrs MUL8m)>; def: InstRW<[BWWriteResGroup91], (instregex "PDEP(32|64)rm")>; def: InstRW<[BWWriteResGroup91], (instregex "PEXT(32|64)rm")>; def: InstRW<[BWWriteResGroup91], (instregex "POPCNT(16|32|64)rm")>; @@ -2638,22 +2638,22 @@ def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup91_16], (instregex "IMUL16rm(i8)?")>; +def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> { let Latency = 8; let NumMicroOps = 5; } -def: InstRW<[BWWriteResGroup91_16_2], (instregex "IMUL16m")>; -def: InstRW<[BWWriteResGroup91_16_2], (instregex "MUL16m")>; +def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m)>; +def: InstRW<[BWWriteResGroup91_16_2], (instrs MUL16m)>; def BWWriteResGroup91_32 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> { let Latency = 8; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[BWWriteResGroup91_32], (instregex "IMUL32m")>; -def: InstRW<[BWWriteResGroup91_32], (instregex "MUL32m")>; +def: InstRW<[BWWriteResGroup91_32], (instrs IMUL32m)>; +def: InstRW<[BWWriteResGroup91_32], (instrs MUL32m)>; def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> { let Latency = 8; @@ -2891,7 +2891,7 @@ def: InstRW<[BWWriteResGroup107], (instregex "CVTTPD2DQrm")>; def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVTPD2PIirm")>; def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVTPI2PDirm")>; def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVTTPD2PIirm")>; -def: InstRW<[BWWriteResGroup107], (instregex "MULX64rm")>; +def: InstRW<[BWWriteResGroup107], (instrs MULX64rm)>; def: InstRW<[BWWriteResGroup107], (instregex "VCVTDQ2PDrm")>; def: InstRW<[BWWriteResGroup107], (instregex "VCVTSD2SSrm")>; @@ -3056,7 +3056,7 @@ def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> { let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } -def: InstRW<[BWWriteResGroup121], (instregex "MULX32rm")>; +def: InstRW<[BWWriteResGroup121], (instrs MULX32rm)>; def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> { let Latency = 11; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 4e2b078f23f..ce30ee804ae 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -1545,9 +1545,9 @@ def: InstRW<[HWWriteResGroup12], (instregex "FCOM32m")>; def: InstRW<[HWWriteResGroup12], (instregex "FCOM64m")>; def: InstRW<[HWWriteResGroup12], (instregex "FCOMP32m")>; def: InstRW<[HWWriteResGroup12], (instregex "FCOMP64m")>; -def: InstRW<[HWWriteResGroup12], (instregex "IMUL(16|32|64)m")>; -def: InstRW<[HWWriteResGroup12], (instregex "IMUL(16|32|64)rm(i8)?")>; -def: InstRW<[HWWriteResGroup12], (instregex "IMUL8m")>; +def: InstRW<[HWWriteResGroup12], (instrs IMUL16m, IMUL32m, IMUL64m)>; +def: InstRW<[HWWriteResGroup12], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8, IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi32, IMUL64rmi8)>; +def: InstRW<[HWWriteResGroup12], (instrs IMUL8m)>; def: InstRW<[HWWriteResGroup12], (instregex "LZCNT(16|32|64)rm")>; def: InstRW<[HWWriteResGroup12], (instregex "MAX(C?)SDrm")>; def: InstRW<[HWWriteResGroup12], (instregex "MAX(C?)SSrm")>; @@ -1556,8 +1556,8 @@ def: InstRW<[HWWriteResGroup12], (instregex "MIN(C?)SSrm")>; def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPI2PSirm")>; def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTPS2PIirm")>; def: InstRW<[HWWriteResGroup12], (instregex "MMX_CVTTPS2PIirm")>; -def: InstRW<[HWWriteResGroup12], (instregex "MUL(16|32|64)m")>; -def: InstRW<[HWWriteResGroup12], (instregex "MUL8m")>; +def: InstRW<[HWWriteResGroup12], (instrs MUL16m, MUL32m, MUL64m)>; +def: InstRW<[HWWriteResGroup12], (instrs MUL8m)>; def: InstRW<[HWWriteResGroup12], (instregex "PDEP(32|64)rm")>; def: InstRW<[HWWriteResGroup12], (instregex "PEXT(32|64)rm")>; def: InstRW<[HWWriteResGroup12], (instregex "POPCNT(16|32|64)rm")>; @@ -2498,8 +2498,8 @@ def: InstRW<[HWWriteResGroup50], (instregex "COMISSrr")>; def: InstRW<[HWWriteResGroup50], (instregex "CVTDQ2PSrr")>; def: InstRW<[HWWriteResGroup50], (instregex "CVTPS2DQrr")>; def: InstRW<[HWWriteResGroup50], (instregex "CVTTPS2DQrr")>; -def: InstRW<[HWWriteResGroup50], (instregex "IMUL64rr(i8)?")>; -def: InstRW<[HWWriteResGroup50], (instregex "IMUL8r")>; +def: InstRW<[HWWriteResGroup50], (instrs IMUL64rr, IMUL64rri32, IMUL64rri8)>; +def: InstRW<[HWWriteResGroup50], (instrs IMUL8r)>; def: InstRW<[HWWriteResGroup50], (instregex "LZCNT(16|32|64)rr")>; def: InstRW<[HWWriteResGroup50], (instregex "MAX(C?)PDrr")>; def: InstRW<[HWWriteResGroup50], (instregex "MAX(C?)PSrr")>; @@ -2510,7 +2510,7 @@ def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)PSrr")>; def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)SDrr")>; def: InstRW<[HWWriteResGroup50], (instregex "MIN(C?)SSrr")>; def: InstRW<[HWWriteResGroup50], (instregex "MMX_CVTPI2PSirr")>; -def: InstRW<[HWWriteResGroup50], (instregex "MUL8r")>; +def: InstRW<[HWWriteResGroup50], (instrs MUL8r)>; def: InstRW<[HWWriteResGroup50], (instregex "PDEP(32|64)rr")>; def: InstRW<[HWWriteResGroup50], (instregex "PEXT(32|64)rr")>; def: InstRW<[HWWriteResGroup50], (instregex "POPCNT(16|32|64)rr")>; @@ -2578,13 +2578,13 @@ def HWWriteResGroup50_16 : SchedWriteRes<[HWPort1, HWPort0156]> { let Latency = 3; let NumMicroOps = 4; } -def: InstRW<[HWWriteResGroup50_16], (instregex "IMUL16rr(i8)?")>; +def: InstRW<[HWWriteResGroup50_16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; def HWWriteResGroup50_32 : SchedWriteRes<[HWPort1, HWPort0156]> { let Latency = 3; let NumMicroOps = 3; } -def: InstRW<[HWWriteResGroup50_32], (instregex "IMUL32rr(i8)?")>; +def: InstRW<[HWWriteResGroup50_32], (instrs IMUL32rr, IMUL32rri, IMUL32rri8)>; def HWWriteResGroup51 : SchedWriteRes<[HWPort5]> { let Latency = 3; @@ -3038,23 +3038,23 @@ def HWWriteResGroup74 : SchedWriteRes<[HWPort1,HWPort6]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[HWWriteResGroup74], (instregex "IMUL64r")>; -def: InstRW<[HWWriteResGroup74], (instregex "MUL64r")>; -def: InstRW<[HWWriteResGroup74], (instregex "MULX64rr")>; +def: InstRW<[HWWriteResGroup74], (instrs IMUL64r)>; +def: InstRW<[HWWriteResGroup74], (instrs MUL64r)>; +def: InstRW<[HWWriteResGroup74], (instrs MULX64rr)>; def HWWriteResGroup74_16 : SchedWriteRes<[HWPort1, HWPort0156]> { let Latency = 4; let NumMicroOps = 4; } -def: InstRW<[HWWriteResGroup74_16], (instregex "IMUL16r")>; -def: InstRW<[HWWriteResGroup74_16], (instregex "MUL16r")>; +def: InstRW<[HWWriteResGroup74_16], (instrs IMUL16r)>; +def: InstRW<[HWWriteResGroup74_16], (instrs MUL16r)>; def HWWriteResGroup74_32 : SchedWriteRes<[HWPort1,HWPort0156]> { let Latency = 4; let NumMicroOps = 3; } -def: InstRW<[HWWriteResGroup74_32], (instregex "IMUL32r")>; -def: InstRW<[HWWriteResGroup74_32], (instregex "MUL32r")>; +def: InstRW<[HWWriteResGroup74_32], (instrs IMUL32r)>; +def: InstRW<[HWWriteResGroup74_32], (instrs MUL32r)>; def HWWriteResGroup75 : SchedWriteRes<[HWPort1,HWPort23]> { let Latency = 11; @@ -3128,7 +3128,7 @@ def HWWriteResGroup79 : SchedWriteRes<[HWPort1,HWPort6,HWPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[HWWriteResGroup79], (instregex "MULX64rm")>; +def: InstRW<[HWWriteResGroup79], (instrs MULX64rm)>; def HWWriteResGroup80 : SchedWriteRes<[HWPort5,HWPort23,HWPort015]> { let Latency = 9; @@ -3424,7 +3424,7 @@ def HWWriteResGroup95 : SchedWriteRes<[HWPort1,HWPort06,HWPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[HWWriteResGroup95], (instregex "MULX32rr")>; +def: InstRW<[HWWriteResGroup95], (instrs MULX32rr)>; def HWWriteResGroup96 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> { let Latency = 11; @@ -3462,7 +3462,7 @@ def HWWriteResGroup98 : SchedWriteRes<[HWPort1,HWPort23,HWPort06,HWPort0156]> { let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } -def: InstRW<[HWWriteResGroup98], (instregex "MULX32rm")>; +def: InstRW<[HWWriteResGroup98], (instrs MULX32rm)>; def HWWriteResGroup99 : SchedWriteRes<[HWPort6,HWPort0156]> { let Latency = 5; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 025240e48ed..bd1a2719536 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -936,7 +936,7 @@ def: InstRW<[SBWriteResGroup21], (instregex "MIN(C?)SSrr")>; def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPI2PSirr")>; def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTPS2PIirr")>; def: InstRW<[SBWriteResGroup21], (instregex "MMX_CVTTPS2PIirr")>; -def: InstRW<[SBWriteResGroup21], (instregex "MUL8r")>; +def: InstRW<[SBWriteResGroup21], (instrs MUL8r)>; def: InstRW<[SBWriteResGroup21], (instregex "POPCNT(16|32|64)rr")>; def: InstRW<[SBWriteResGroup21], (instregex "PUSHFS64")>; def: InstRW<[SBWriteResGroup21], (instregex "ROUNDPDr")>; @@ -1111,7 +1111,7 @@ def SBWriteResGroup27 : SchedWriteRes<[SBPort0,SBPort1]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SBWriteResGroup27], (instregex "MUL(16|32|64)r")>; +def: InstRW<[SBWriteResGroup27], (instrs MUL16r, MUL32r, MUL64r)>; def SBWriteResGroup28 : SchedWriteRes<[SBPort1,SBPort5]> { let Latency = 4; @@ -1962,7 +1962,7 @@ def: InstRW<[SBWriteResGroup72], (instregex "FCOM32m")>; def: InstRW<[SBWriteResGroup72], (instregex "FCOM64m")>; def: InstRW<[SBWriteResGroup72], (instregex "FCOMP32m")>; def: InstRW<[SBWriteResGroup72], (instregex "FCOMP64m")>; -def: InstRW<[SBWriteResGroup72], (instregex "MUL8m")>; +def: InstRW<[SBWriteResGroup72], (instrs MUL8m)>; def SBWriteResGroup73 : SchedWriteRes<[SBPort5,SBPort23]> { let Latency = 8; @@ -2272,7 +2272,7 @@ def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SI64rm")>; def: InstRW<[SBWriteResGroup93], (instregex "CVTTSD2SIrm")>; def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SI64rm")>; def: InstRW<[SBWriteResGroup93], (instregex "CVTTSS2SIrm")>; -def: InstRW<[SBWriteResGroup93], (instregex "MUL(16|32|64)m")>; +def: InstRW<[SBWriteResGroup93], (instrs MUL16m, MUL32m, MUL64m)>; def SBWriteResGroup94 : SchedWriteRes<[SBPort0,SBPort5,SBPort23]> { let Latency = 9; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 7135f8b2a7d..1ff268aa1c5 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -1214,10 +1214,10 @@ def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { } def: InstRW<[SKLWriteResGroup29], (instregex "BSF(16|32|64)rr")>; def: InstRW<[SKLWriteResGroup29], (instregex "BSR(16|32|64)rr")>; -def: InstRW<[SKLWriteResGroup29], (instregex "IMUL64rr(i8)?")>; -def: InstRW<[SKLWriteResGroup29], (instregex "IMUL8r")>; +def: InstRW<[SKLWriteResGroup29], (instrs IMUL64rr, IMUL64rri32, IMUL64rri8)>; +def: InstRW<[SKLWriteResGroup29], (instrs IMUL8r)>; def: InstRW<[SKLWriteResGroup29], (instregex "LZCNT(16|32|64)rr")>; -def: InstRW<[SKLWriteResGroup29], (instregex "MUL8r")>; +def: InstRW<[SKLWriteResGroup29], (instrs MUL8r)>; def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr")>; def: InstRW<[SKLWriteResGroup29], (instregex "PEXT(32|64)rr")>; def: InstRW<[SKLWriteResGroup29], (instregex "POPCNT(16|32|64)rr")>; @@ -1230,13 +1230,13 @@ def SKLWriteResGroup29_16 : SchedWriteRes<[SKLPort1, SKLPort0156]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup29_16], (instregex "IMUL16rr(i8)?")>; +def: InstRW<[SKLWriteResGroup29_16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; def SKLWriteResGroup29_32 : SchedWriteRes<[SKLPort1]> { let Latency = 3; let NumMicroOps = 1; } -def: InstRW<[SKLWriteResGroup29_32], (instregex "IMUL32rr(i8)?")>; +def: InstRW<[SKLWriteResGroup29_32], (instrs IMUL32rr, IMUL32rri, IMUL32rri8)>; def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { let Latency = 3; @@ -1620,16 +1620,16 @@ def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKLWriteResGroup51], (instregex "IMUL64r")>; -def: InstRW<[SKLWriteResGroup51], (instregex "MUL64r")>; -def: InstRW<[SKLWriteResGroup51], (instregex "MULX64rr")>; +def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r)>; +def: InstRW<[SKLWriteResGroup51], (instrs MUL64r)>; +def: InstRW<[SKLWriteResGroup51], (instrs MULX64rr)>; def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { let Latency = 4; let NumMicroOps = 4; } -def: InstRW<[SKLWriteResGroup51_16], (instregex "IMUL16r")>; -def: InstRW<[SKLWriteResGroup51_16], (instregex "MUL16r")>; +def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r)>; +def: InstRW<[SKLWriteResGroup51_16], (instrs MUL16r)>; def SKLWriteResGroup52 : SchedWriteRes<[SKLPort5,SKLPort01]> { let Latency = 4; @@ -1771,9 +1771,9 @@ def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup62], (instregex "IMUL32r")>; -def: InstRW<[SKLWriteResGroup62], (instregex "MUL32r")>; -def: InstRW<[SKLWriteResGroup62], (instregex "MULX32rr")>; +def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r)>; +def: InstRW<[SKLWriteResGroup62], (instrs MUL32r)>; +def: InstRW<[SKLWriteResGroup62], (instrs MULX32rr)>; def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { let Latency = 5; @@ -2575,9 +2575,9 @@ def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { } def: InstRW<[SKLWriteResGroup107], (instregex "BSF(16|32|64)rm")>; def: InstRW<[SKLWriteResGroup107], (instregex "BSR(16|32|64)rm")>; -def: InstRW<[SKLWriteResGroup107], (instregex "IMUL64m")>; -def: InstRW<[SKLWriteResGroup107], (instregex "IMUL(32|64)rm(i8)?")>; -def: InstRW<[SKLWriteResGroup107], (instregex "IMUL8m")>; +def: InstRW<[SKLWriteResGroup107], (instrs IMUL64m)>; +def: InstRW<[SKLWriteResGroup107], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi32, IMUL64rmi8)>; +def: InstRW<[SKLWriteResGroup107], (instrs IMUL8m)>; def: InstRW<[SKLWriteResGroup107], (instregex "LZCNT(16|32|64)rm")>; def: InstRW<[SKLWriteResGroup107], (instregex "MUL(16|32|64)m")>; def: InstRW<[SKLWriteResGroup107], (instregex "MUL8m")>; @@ -2587,26 +2587,26 @@ def: InstRW<[SKLWriteResGroup107], (instregex "POPCNT(16|32|64)rm")>; def: InstRW<[SKLWriteResGroup107], (instregex "TZCNT(16|32|64)rm")>; def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> { - let Latency = 3; + let Latency = 8; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup107_16], (instregex "IMUL16rm(i8)?")>; +def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> { - let Latency = 3; + let Latency = 8; let NumMicroOps = 5; } -def: InstRW<[SKLWriteResGroup107_16_2], (instregex "IMUL16m")>; -def: InstRW<[SKLWriteResGroup107_16_2], (instregex "MUL16m")>; +def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m)>; +def: InstRW<[SKLWriteResGroup107_16_2], (instrs MUL16m)>; def SKLWriteResGroup107_32 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> { - let Latency = 3; + let Latency = 8; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup107_32], (instregex "IMUL32m")>; -def: InstRW<[SKLWriteResGroup107_32], (instregex "MUL32m")>; +def: InstRW<[SKLWriteResGroup107_32], (instrs IMUL32m)>; +def: InstRW<[SKLWriteResGroup107_32], (instrs MUL32m)>; def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { let Latency = 8; @@ -2941,7 +2941,7 @@ def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKLWriteResGroup127], (instregex "MULX64rm")>; +def: InstRW<[SKLWriteResGroup127], (instrs MULX64rm)>; def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { let Latency = 9; @@ -3155,7 +3155,7 @@ def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort015 let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } -def: InstRW<[SKLWriteResGroup142], (instregex "MULX32rm")>; +def: InstRW<[SKLWriteResGroup142], (instrs MULX32rm)>; def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { let Latency = 10; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index b934022bf8c..44ba5b44c07 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -1758,10 +1758,10 @@ def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> { } def: InstRW<[SKXWriteResGroup31], (instregex "BSF(16|32|64)rr")>; def: InstRW<[SKXWriteResGroup31], (instregex "BSR(16|32|64)rr")>; -def: InstRW<[SKXWriteResGroup31], (instregex "IMUL64rr(i8)?")>; -def: InstRW<[SKXWriteResGroup31], (instregex "IMUL8r")>; +def: InstRW<[SKXWriteResGroup31], (instrs IMUL64rr, IMUL64rri32, IMUL64rri8)>; +def: InstRW<[SKXWriteResGroup31], (instrs IMUL8r)>; def: InstRW<[SKXWriteResGroup31], (instregex "LZCNT(16|32|64)rr")>; -def: InstRW<[SKXWriteResGroup31], (instregex "MUL8r")>; +def: InstRW<[SKXWriteResGroup31], (instrs MUL8r)>; def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr")>; def: InstRW<[SKXWriteResGroup31], (instregex "PEXT(32|64)rr")>; def: InstRW<[SKXWriteResGroup31], (instregex "POPCNT(16|32|64)rr")>; @@ -1774,13 +1774,13 @@ def SKXWriteResGroup31_16 : SchedWriteRes<[SKXPort1, SKXPort0156]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup31_16], (instregex "IMUL16rr(i8)?")>; +def: InstRW<[SKXWriteResGroup31_16], (instrs IMUL16rr, IMUL16rri, IMUL16rri8)>; def SKXWriteResGroup31_32 : SchedWriteRes<[SKXPort1]> { let Latency = 3; let NumMicroOps = 1; } -def: InstRW<[SKXWriteResGroup31_32], (instregex "IMUL32rr(i8)?")>; +def: InstRW<[SKXWriteResGroup31_32], (instrs IMUL32rr, IMUL32rri, IMUL32rri8)>; def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> { let Latency = 3; @@ -2654,16 +2654,16 @@ def SKXWriteResGroup52 : SchedWriteRes<[SKXPort1,SKXPort5]> { let NumMicroOps = 2; let ResourceCycles = [1,1]; } -def: InstRW<[SKXWriteResGroup52], (instregex "IMUL(32|64)r")>; -def: InstRW<[SKXWriteResGroup52], (instregex "MUL(32|64)r")>; -def: InstRW<[SKXWriteResGroup52], (instregex "MULX64rr")>; +def: InstRW<[SKXWriteResGroup52], (instrs IMUL32r, IMUL64r)>; +def: InstRW<[SKXWriteResGroup52], (instrs MUL32r, MUL64r)>; +def: InstRW<[SKXWriteResGroup52], (instrs MULX64rr)>; def SKXWriteResGroup52_16 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { let Latency = 4; let NumMicroOps = 4; } -def: InstRW<[SKXWriteResGroup52_16], (instregex "IMUL16r")>; -def: InstRW<[SKXWriteResGroup52_16], (instregex "MUL16r")>; +def: InstRW<[SKXWriteResGroup52_16], (instrs IMUL16r)>; +def: InstRW<[SKXWriteResGroup52_16], (instrs MUL16r)>; def SKXWriteResGroup53 : SchedWriteRes<[SKXPort5,SKXPort01]> { let Latency = 4; @@ -2856,7 +2856,7 @@ def SKXWriteResGroup64 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup64], (instregex "MULX32rr")>; +def: InstRW<[SKXWriteResGroup64], (instrs MULX32rr)>; def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> { let Latency = 5; @@ -4033,12 +4033,12 @@ def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> { } def: InstRW<[SKXWriteResGroup118], (instregex "BSF(16|32|64)rm")>; def: InstRW<[SKXWriteResGroup118], (instregex "BSR(16|32|64)rm")>; -def: InstRW<[SKXWriteResGroup118], (instregex "IMUL64m")>; -def: InstRW<[SKXWriteResGroup118], (instregex "IMUL(32|64)rm(i8)?")>; -def: InstRW<[SKXWriteResGroup118], (instregex "IMUL8m")>; +def: InstRW<[SKXWriteResGroup118], (instrs IMUL64m)>; +def: InstRW<[SKXWriteResGroup118], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi32, IMUL64rmi8)>; +def: InstRW<[SKXWriteResGroup118], (instrs IMUL8m)>; def: InstRW<[SKXWriteResGroup118], (instregex "LZCNT(16|32|64)rm")>; -def: InstRW<[SKXWriteResGroup118], (instregex "MUL(16|32|64)m")>; -def: InstRW<[SKXWriteResGroup118], (instregex "MUL8m")>; +def: InstRW<[SKXWriteResGroup118], (instrs MUL16m, MUL32m, MUL64m)>; +def: InstRW<[SKXWriteResGroup118], (instrs MUL8m)>; def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm")>; def: InstRW<[SKXWriteResGroup118], (instregex "PEXT(32|64)rm")>; def: InstRW<[SKXWriteResGroup118], (instregex "POPCNT(16|32|64)rm")>; @@ -4049,22 +4049,22 @@ def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup118_16_1], (instregex "IMUL16rm(i8)?")>; +def: InstRW<[SKXWriteResGroup118_16_1], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>; def SKXWriteResGroup118_16_2 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> { let Latency = 8; let NumMicroOps = 5; } -def: InstRW<[SKXWriteResGroup118_16_2], (instregex "IMUL16m")>; -def: InstRW<[SKXWriteResGroup118_16_2], (instregex "MUL16m")>; +def: InstRW<[SKXWriteResGroup118_16_2], (instrs IMUL16m)>; +def: InstRW<[SKXWriteResGroup118_16_2], (instrs MUL16m)>; def SKXWriteResGroup118_32 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> { let Latency = 8; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup118_32], (instregex "IMUL32m")>; -def: InstRW<[SKXWriteResGroup118_32], (instregex "MUL32m")>; +def: InstRW<[SKXWriteResGroup118_32], (instrs IMUL32m)>; +def: InstRW<[SKXWriteResGroup118_32], (instrs MUL32m)>; def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { let Latency = 8; @@ -4804,7 +4804,7 @@ def SKXWriteResGroup142 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort23]> { let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } -def: InstRW<[SKXWriteResGroup142], (instregex "MULX64rm")>; +def: InstRW<[SKXWriteResGroup142], (instrs MULX64rm)>; def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { let Latency = 9; @@ -5232,7 +5232,7 @@ def SKXWriteResGroup156 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort06,SKXPort015 let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } -def: InstRW<[SKXWriteResGroup156], (instregex "MULX32rm")>; +def: InstRW<[SKXWriteResGroup156], (instrs MULX32rm)>; def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { let Latency = 10; diff --git a/llvm/test/CodeGen/X86/schedule-x86_64.ll b/llvm/test/CodeGen/X86/schedule-x86_64.ll index 38874dd6d1a..dda4d7b8f2e 100644 --- a/llvm/test/CodeGen/X86/schedule-x86_64.ll +++ b/llvm/test/CodeGen/X86/schedule-x86_64.ll @@ -5707,13 +5707,13 @@ define void @test_imul_16(i16 %a0, i16* %a1) optsize { ; BROADWELL-NEXT: imulw %di # sched: [4:1.00] ; BROADWELL-NEXT: imulw (%rsi) # sched: [8:1.00] ; BROADWELL-NEXT: imulw %di, %di # sched: [3:1.00] -; BROADWELL-NEXT: imulw (%rsi), %di # sched: [4:1.00] +; BROADWELL-NEXT: imulw (%rsi), %di # sched: [8:1.00] ; BROADWELL-NEXT: imulw $511, %di, %di # imm = 0x1FF ; BROADWELL-NEXT: # sched: [3:1.00] ; BROADWELL-NEXT: imulw $511, (%rsi), %di # imm = 0x1FF -; BROADWELL-NEXT: # sched: [4:1.00] +; BROADWELL-NEXT: # sched: [8:1.00] ; BROADWELL-NEXT: imulw $7, %di, %di # sched: [3:1.00] -; BROADWELL-NEXT: imulw $7, (%rsi), %di # sched: [4:1.00] +; BROADWELL-NEXT: imulw $7, (%rsi), %di # sched: [8:1.00] ; BROADWELL-NEXT: #NO_APP ; BROADWELL-NEXT: retq # sched: [7:1.00] ; @@ -5721,15 +5721,15 @@ define void @test_imul_16(i16 %a0, i16* %a1) optsize { ; SKYLAKE: # %bb.0: ; SKYLAKE-NEXT: #APP ; SKYLAKE-NEXT: imulw %di # sched: [4:1.00] -; SKYLAKE-NEXT: imulw (%rsi) # sched: [3:1.00] +; SKYLAKE-NEXT: imulw (%rsi) # sched: [8:1.00] ; SKYLAKE-NEXT: imulw %di, %di # sched: [3:1.00] -; SKYLAKE-NEXT: imulw (%rsi), %di # sched: [4:1.00] +; SKYLAKE-NEXT: imulw (%rsi), %di # sched: [8:1.00] ; SKYLAKE-NEXT: imulw $511, %di, %di # imm = 0x1FF ; SKYLAKE-NEXT: # sched: [3:1.00] ; SKYLAKE-NEXT: imulw $511, (%rsi), %di # imm = 0x1FF -; SKYLAKE-NEXT: # sched: [4:1.00] +; SKYLAKE-NEXT: # sched: [8:1.00] ; SKYLAKE-NEXT: imulw $7, %di, %di # sched: [3:1.00] -; SKYLAKE-NEXT: imulw $7, (%rsi), %di # sched: [4:1.00] +; SKYLAKE-NEXT: imulw $7, (%rsi), %di # sched: [8:1.00] ; SKYLAKE-NEXT: #NO_APP ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; @@ -5739,13 +5739,13 @@ define void @test_imul_16(i16 %a0, i16* %a1) optsize { ; SKX-NEXT: imulw %di # sched: [4:1.00] ; SKX-NEXT: imulw (%rsi) # sched: [8:1.00] ; SKX-NEXT: imulw %di, %di # sched: [3:1.00] -; SKX-NEXT: imulw (%rsi), %di # sched: [4:1.00] +; SKX-NEXT: imulw (%rsi), %di # sched: [8:1.00] ; SKX-NEXT: imulw $511, %di, %di # imm = 0x1FF ; SKX-NEXT: # sched: [3:1.00] ; SKX-NEXT: imulw $511, (%rsi), %di # imm = 0x1FF -; SKX-NEXT: # sched: [4:1.00] +; SKX-NEXT: # sched: [8:1.00] ; SKX-NEXT: imulw $7, %di, %di # sched: [3:1.00] -; SKX-NEXT: imulw $7, (%rsi), %di # sched: [4:1.00] +; SKX-NEXT: imulw $7, (%rsi), %di # sched: [8:1.00] ; SKX-NEXT: #NO_APP ; SKX-NEXT: retq # sched: [7:1.00] ; @@ -5870,13 +5870,13 @@ define void @test_imul_32(i32 %a0, i32* %a1) optsize { ; BROADWELL-NEXT: imull %edi # sched: [4:1.00] ; BROADWELL-NEXT: imull (%rsi) # sched: [8:1.00] ; BROADWELL-NEXT: imull %edi, %edi # sched: [3:1.00] -; BROADWELL-NEXT: imull (%rsi), %edi # sched: [4:1.00] +; BROADWELL-NEXT: imull (%rsi), %edi # sched: [8:1.00] ; BROADWELL-NEXT: imull $665536, %edi, %edi # imm = 0xA27C0 ; BROADWELL-NEXT: # sched: [3:1.00] ; BROADWELL-NEXT: imull $665536, (%rsi), %edi # imm = 0xA27C0 -; BROADWELL-NEXT: # sched: [4:1.00] +; BROADWELL-NEXT: # sched: [8:1.00] ; BROADWELL-NEXT: imull $7, %edi, %edi # sched: [3:1.00] -; BROADWELL-NEXT: imull $7, (%rsi), %edi # sched: [4:1.00] +; BROADWELL-NEXT: imull $7, (%rsi), %edi # sched: [8:1.00] ; BROADWELL-NEXT: #NO_APP ; BROADWELL-NEXT: retq # sched: [7:1.00] ; @@ -5884,15 +5884,15 @@ define void @test_imul_32(i32 %a0, i32* %a1) optsize { ; SKYLAKE: # %bb.0: ; SKYLAKE-NEXT: #APP ; SKYLAKE-NEXT: imull %edi # sched: [5:1.00] -; SKYLAKE-NEXT: imull (%rsi) # sched: [3:1.00] +; SKYLAKE-NEXT: imull (%rsi) # sched: [8:1.00] ; SKYLAKE-NEXT: imull %edi, %edi # sched: [3:1.00] -; SKYLAKE-NEXT: imull (%rsi), %edi # sched: [5:1.00] +; SKYLAKE-NEXT: imull (%rsi), %edi # sched: [8:1.00] ; SKYLAKE-NEXT: imull $665536, %edi, %edi # imm = 0xA27C0 ; SKYLAKE-NEXT: # sched: [3:1.00] ; SKYLAKE-NEXT: imull $665536, (%rsi), %edi # imm = 0xA27C0 -; SKYLAKE-NEXT: # sched: [5:1.00] +; SKYLAKE-NEXT: # sched: [8:1.00] ; SKYLAKE-NEXT: imull $7, %edi, %edi # sched: [3:1.00] -; SKYLAKE-NEXT: imull $7, (%rsi), %edi # sched: [5:1.00] +; SKYLAKE-NEXT: imull $7, (%rsi), %edi # sched: [8:1.00] ; SKYLAKE-NEXT: #NO_APP ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; @@ -5902,13 +5902,13 @@ define void @test_imul_32(i32 %a0, i32* %a1) optsize { ; SKX-NEXT: imull %edi # sched: [4:1.00] ; SKX-NEXT: imull (%rsi) # sched: [8:1.00] ; SKX-NEXT: imull %edi, %edi # sched: [3:1.00] -; SKX-NEXT: imull (%rsi), %edi # sched: [4:1.00] +; SKX-NEXT: imull (%rsi), %edi # sched: [8:1.00] ; SKX-NEXT: imull $665536, %edi, %edi # imm = 0xA27C0 ; SKX-NEXT: # sched: [3:1.00] ; SKX-NEXT: imull $665536, (%rsi), %edi # imm = 0xA27C0 -; SKX-NEXT: # sched: [4:1.00] +; SKX-NEXT: # sched: [8:1.00] ; SKX-NEXT: imull $7, %edi, %edi # sched: [3:1.00] -; SKX-NEXT: imull $7, (%rsi), %edi # sched: [4:1.00] +; SKX-NEXT: imull $7, (%rsi), %edi # sched: [8:1.00] ; SKX-NEXT: #NO_APP ; SKX-NEXT: retq # sched: [7:1.00] ; @@ -6033,13 +6033,13 @@ define void @test_imul_64(i64 %a0, i64* %a1) optsize { ; BROADWELL-NEXT: imulq %rdi # sched: [4:1.00] ; BROADWELL-NEXT: imulq (%rsi) # sched: [8:1.00] ; BROADWELL-NEXT: imulq %rdi, %rdi # sched: [3:1.00] -; BROADWELL-NEXT: imulq (%rsi), %rdi # sched: [4:1.00] +; BROADWELL-NEXT: imulq (%rsi), %rdi # sched: [8:1.00] ; BROADWELL-NEXT: imulq $665536, %rdi, %rdi # imm = 0xA27C0 ; BROADWELL-NEXT: # sched: [3:1.00] ; BROADWELL-NEXT: imulq $665536, (%rsi), %rdi # imm = 0xA27C0 -; BROADWELL-NEXT: # sched: [4:1.00] +; BROADWELL-NEXT: # sched: [8:1.00] ; BROADWELL-NEXT: imulq $7, %rdi, %rdi # sched: [3:1.00] -; BROADWELL-NEXT: imulq $7, (%rsi), %rdi # sched: [4:1.00] +; BROADWELL-NEXT: imulq $7, (%rsi), %rdi # sched: [8:1.00] ; BROADWELL-NEXT: #NO_APP ; BROADWELL-NEXT: retq # sched: [7:1.00] ; @@ -6049,13 +6049,13 @@ define void @test_imul_64(i64 %a0, i64* %a1) optsize { ; SKYLAKE-NEXT: imulq %rdi # sched: [4:1.00] ; SKYLAKE-NEXT: imulq (%rsi) # sched: [8:1.00] ; SKYLAKE-NEXT: imulq %rdi, %rdi # sched: [3:1.00] -; SKYLAKE-NEXT: imulq (%rsi), %rdi # sched: [4:1.00] +; SKYLAKE-NEXT: imulq (%rsi), %rdi # sched: [8:1.00] ; SKYLAKE-NEXT: imulq $665536, %rdi, %rdi # imm = 0xA27C0 ; SKYLAKE-NEXT: # sched: [3:1.00] ; SKYLAKE-NEXT: imulq $665536, (%rsi), %rdi # imm = 0xA27C0 -; SKYLAKE-NEXT: # sched: [4:1.00] +; SKYLAKE-NEXT: # sched: [8:1.00] ; SKYLAKE-NEXT: imulq $7, %rdi, %rdi # sched: [3:1.00] -; SKYLAKE-NEXT: imulq $7, (%rsi), %rdi # sched: [4:1.00] +; SKYLAKE-NEXT: imulq $7, (%rsi), %rdi # sched: [8:1.00] ; SKYLAKE-NEXT: #NO_APP ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; @@ -6065,13 +6065,13 @@ define void @test_imul_64(i64 %a0, i64* %a1) optsize { ; SKX-NEXT: imulq %rdi # sched: [4:1.00] ; SKX-NEXT: imulq (%rsi) # sched: [8:1.00] ; SKX-NEXT: imulq %rdi, %rdi # sched: [3:1.00] -; SKX-NEXT: imulq (%rsi), %rdi # sched: [4:1.00] +; SKX-NEXT: imulq (%rsi), %rdi # sched: [8:1.00] ; SKX-NEXT: imulq $665536, %rdi, %rdi # imm = 0xA27C0 ; SKX-NEXT: # sched: [3:1.00] ; SKX-NEXT: imulq $665536, (%rsi), %rdi # imm = 0xA27C0 -; SKX-NEXT: # sched: [4:1.00] +; SKX-NEXT: # sched: [8:1.00] ; SKX-NEXT: imulq $7, %rdi, %rdi # sched: [3:1.00] -; SKX-NEXT: imulq $7, (%rsi), %rdi # sched: [4:1.00] +; SKX-NEXT: imulq $7, (%rsi), %rdi # sched: [8:1.00] ; SKX-NEXT: #NO_APP ; SKX-NEXT: retq # sched: [7:1.00] ; |
