diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 23 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMScheduleR52.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 11 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.h | 6 |
4 files changed, 17 insertions, 24 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index eeab6e443c7..25b9802f541 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -323,8 +323,9 @@ def FeatureNoNegativeImmediates def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", "Use the MachineScheduler">; -def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler", - "UsePostRAScheduler", "true", "Schedule again after register allocation">; +def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", + "DisablePostRAScheduler", "true", + "Don't schedule again after register allocation">; //===----------------------------------------------------------------------===// // ARM architecture class @@ -829,7 +830,8 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, FeatureSlowLoadDSubreg, FeatureSlowVGETLNi32, FeatureSlowVDUP32, - FeatureUseMISched]>; + FeatureUseMISched, + FeatureNoPostRASched]>; def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, FeatureHasRetAddrStack, @@ -876,8 +878,7 @@ def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, def : ProcessorModel<"cortex-m3", CortexM3Model, [ARMv7m, ProcM3, - FeatureHasNoBranchPredictor, - FeaturePostRAScheduler]>; + FeatureHasNoBranchPredictor]>; def : ProcessorModel<"sc300", CortexM3Model, [ARMv7m, ProcM3, @@ -887,13 +888,11 @@ def : ProcessorModel<"cortex-m4", CortexM3Model, [ARMv7em, FeatureVFP4, FeatureVFPOnlySP, FeatureD16, - FeatureHasNoBranchPredictor, - FeaturePostRAScheduler]>; + FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-m7", [ARMv7em, FeatureFPARMv8, - FeatureD16, - FeaturePostRAScheduler]>; + FeatureD16]>; def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, FeatureNoMovt]>; @@ -903,8 +902,7 @@ def : ProcessorModel<"cortex-m33", CortexM3Model, [ARMv8mMainline, FeatureFPARMv8, FeatureD16, FeatureVFPOnlySP, - FeatureHasNoBranchPredictor, - FeaturePostRAScheduler]>; + FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-a32", [ARMv8a, FeatureHWDivThumb, @@ -968,7 +966,8 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasSlowFPVMLx, FeatureCrypto, FeatureUseMISched, - FeatureZCZeroing]>; + FeatureZCZeroing, + FeatureNoPostRASched]>; def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, FeatureHWDivThumb, diff --git a/llvm/lib/Target/ARM/ARMScheduleR52.td b/llvm/lib/Target/ARM/ARMScheduleR52.td index 782be9b60a7..ca3172808d3 100644 --- a/llvm/lib/Target/ARM/ARMScheduleR52.td +++ b/llvm/lib/Target/ARM/ARMScheduleR52.td @@ -24,7 +24,6 @@ def CortexR52Model : SchedMachineModel { let IssueWidth = 2; // 2 micro-ops dispatched per cycle let LoadLatency = 1; // Optimistic, assuming no misses let MispredictPenalty = 8; // A branch direction mispredict, including PFU - let PostRAScheduler = 1; // Enable PostRA scheduler pass. let CompleteModel = 0; // Covers instructions applicable to cortex-r52. } diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 992d2a34aa0..e440957269f 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -366,15 +366,10 @@ bool ARMSubtarget::enableMachineScheduler() const { // This overrides the PostRAScheduler bit in the SchedModel for any CPU. bool ARMSubtarget::enablePostRAScheduler() const { - if (usePostRAScheduler()) - return true; - if (SchedModel.PostRAScheduler) - return true; - // No need for PostRA scheduling on subtargets where we use the - // MachineScheduler. - if (useMachineScheduler()) + if (disablePostRAScheduler()) return false; - return (!isThumb() || hasThumb2()); + // Don't reschedule potential IT blocks. + return !isThumb1Only(); } bool ARMSubtarget::enableAtomicExpand() const { return hasAnyDataBarrier(); } diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index eb75ddcf323..c57c4e7dcd3 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -194,9 +194,9 @@ protected: /// UseMISched - True if MachineScheduler should be used for this subtarget. bool UseMISched = false; - /// UsePostRAScheduler - True if scheduling should happen again after + /// DisablePostRAScheduler - False if scheduling should happen again after /// register allocation. - bool UsePostRAScheduler = false; + bool DisablePostRAScheduler = false; /// HasThumb2 - True if Thumb2 instructions are supported. bool HasThumb2 = false; @@ -667,7 +667,7 @@ public: bool isRWPI() const; bool useMachineScheduler() const { return UseMISched; } - bool usePostRAScheduler() const { return UsePostRAScheduler; } + bool disablePostRAScheduler() const { return DisablePostRAScheduler; } bool useSoftFloat() const { return UseSoftFloat; } bool isThumb() const { return InThumbMode; } bool isThumb1Only() const { return InThumbMode && !HasThumb2; } |
