diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/schedule-x86_32.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/schedule-x86_64.ll | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index c43dae41c7e..6b867c5c22e 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -474,7 +474,7 @@ def : InstRW<[ZnWriteDiv64], (instregex "DIV64r", "IDIV64r")>; // J(E|R)CXZ. def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>; -def : InstRW<[ZnWriteJCXZ], (instregex "JCXZ", "JECXZ_(32|64)", "JRCXZ")>; +def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>; // INTO def : InstRW<[WriteMicrocoded], (instregex "INTO")>; diff --git a/llvm/test/CodeGen/X86/schedule-x86_32.ll b/llvm/test/CodeGen/X86/schedule-x86_32.ll index 1179300df93..601b4234ad2 100644 --- a/llvm/test/CodeGen/X86/schedule-x86_32.ll +++ b/llvm/test/CodeGen/X86/schedule-x86_32.ll @@ -1348,7 +1348,7 @@ define void @test_jcxz_jecxz() optsize { ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: JXTGT: ; ZNVER1-NEXT: jcxz JXTGT # sched: [1:0.50] -; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.25] +; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retl # sched: [1:0.50] call void asm sideeffect "JXTGT: \0A\09 jcxz JXTGT \0A\09 jecxz JXTGT", ""() diff --git a/llvm/test/CodeGen/X86/schedule-x86_64.ll b/llvm/test/CodeGen/X86/schedule-x86_64.ll index 0ee3b332e42..01972522571 100644 --- a/llvm/test/CodeGen/X86/schedule-x86_64.ll +++ b/llvm/test/CodeGen/X86/schedule-x86_64.ll @@ -7279,7 +7279,7 @@ define void @test_jecxz_jrcxz() optsize { ; ZNVER1: # %bb.0: ; ZNVER1-NEXT: #APP ; ZNVER1-NEXT: JXTGT: -; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.25] +; ZNVER1-NEXT: jecxz JXTGT # sched: [1:0.50] ; ZNVER1-NEXT: jrcxz JXTGT # sched: [1:0.50] ; ZNVER1-NEXT: #NO_APP ; ZNVER1-NEXT: retq # sched: [1:0.50] |
