diff options
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 31 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/memcmp.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/x86-shrink-wrapping.ll | 3 |
3 files changed, 35 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 198b48fe9d4..2dc71f100d0 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -3927,6 +3927,26 @@ bool X86::isCalleePop(CallingConv::ID CallingConv, } } +/// \brief Return true if the condition is an unsigned comparison operation. +static bool isX86CCUnsigned(unsigned X86CC) { + switch (X86CC) { + default: + llvm_unreachable("Invalid integer condition!"); + case X86::COND_E: + case X86::COND_NE: + case X86::COND_B: + case X86::COND_A: + case X86::COND_BE: + case X86::COND_AE: + return true; + case X86::COND_G: + case X86::COND_GE: + case X86::COND_L: + case X86::COND_LE: + return false; + } +} + static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) { switch (SetCCOpcode) { default: llvm_unreachable("Invalid integer condition!"); @@ -14746,6 +14766,17 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 || Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) { + // Only promote the compare up to I32 if it is a 16 bit operation + // with an immediate. 16 bit immediates are to be avoided. + if ((Op0.getValueType() == MVT::i16 && + (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) && + !DAG.getMachineFunction().getFunction()->optForMinSize() && + !Subtarget.isAtom()) { + unsigned ExtendOp = + isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; + Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0); + Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1); + } // Use SUB instead of CMP to enable CSE between SUB and CMP. SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32); SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs, diff --git a/llvm/test/CodeGen/X86/memcmp.ll b/llvm/test/CodeGen/X86/memcmp.ll index 410741ba4d3..51ce5dc8960 100644 --- a/llvm/test/CodeGen/X86/memcmp.ll +++ b/llvm/test/CodeGen/X86/memcmp.ll @@ -41,7 +41,8 @@ bb: ; preds = %entry return: ; preds = %entry ret void ; CHECK-LABEL: memcmp2a: -; CHECK: cmpw $28527, (% +; CHECK: movzwl +; CHECK-NEXT: cmpl $28527, } diff --git a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll index df45e14e91a..5b6e773fe5d 100644 --- a/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll +++ b/llvm/test/CodeGen/X86/x86-shrink-wrapping.ll @@ -520,7 +520,8 @@ declare hidden fastcc %struct.temp_slot* @find_temp_slot_from_address(%struct.rt ; CHECK: testq %rdi, %rdi ; CHECK-NEXT: je [[CLEANUP:LBB[0-9_]+]] ; -; CHECK: cmpw $66, (%rdi) +; CHECK: movzwl (%rdi), [[BF_LOAD:%e[a-z]+]] +; CHECK-NEXT: cmpl $66, [[BF_LOAD]] ; CHECK-NEXT: jne [[CLEANUP]] ; ; CHECK: movq 8(%rdi), %rdi |
