diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Hexagon/inst_xor.ll | 10 |
3 files changed, 16 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 13e1e6dd27a..1688c4ad3fb 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1307,10 +1307,12 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::A2_porfnew: case Hexagon::A2_port: case Hexagon::A2_portnew: + case Hexagon::A2_pxorf: + case Hexagon::A2_pxorfnew: + case Hexagon::A2_pxort: + case Hexagon::A2_pxortnew: case Hexagon::ADD_ri_cPt: case Hexagon::ADD_ri_cNotPt: - case Hexagon::XOR_rr_cPt: - case Hexagon::XOR_rr_cNotPt: case Hexagon::SUB_rr_cPt: case Hexagon::SUB_rr_cNotPt: case Hexagon::COMBINE_rr_cPt: diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 9238e816317..4090681c30d 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -165,6 +165,7 @@ defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>; defm and : T_ALU32_3op_A2<"and", 0b001, 0b000, 0, 1>; defm or : T_ALU32_3op_A2<"or", 0b001, 0b001, 0, 1>; defm sub : T_ALU32_3op_A2<"sub", 0b011, 0b001, 1, 0>; +defm xor : T_ALU32_3op_A2<"xor", 0b001, 0b011, 0, 1>; // Pats for instruction selection. class BinOp32_pat<SDNode Op, InstHexagon MI, ValueType ResT> @@ -175,6 +176,7 @@ def: BinOp32_pat<add, A2_add, i32>; def: BinOp32_pat<and, A2_and, i32>; def: BinOp32_pat<or, A2_or, i32>; def: BinOp32_pat<sub, A2_sub, i32>; +def: BinOp32_pat<xor, A2_xor, i32>; multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot, bit isPredNew> { @@ -211,10 +213,6 @@ multiclass ALU32_base<string mnemonic, string CextOp, SDNode OpNode> { } } -let isCommutable = 1 in { - defm XOR_rr : ALU32_base<"xor", "XOR", xor>, ImmRegRel, PredNewRel; -} - defm SUB_rr : ALU32_base<"sub", "SUB", sub>, ImmRegRel, PredNewRel; // Combines the two integer registers SRC1 and SRC2 into a double register. diff --git a/llvm/test/MC/Hexagon/inst_xor.ll b/llvm/test/MC/Hexagon/inst_xor.ll new file mode 100644 index 00000000000..fe989e50385 --- /dev/null +++ b/llvm/test/MC/Hexagon/inst_xor.ll @@ -0,0 +1,10 @@ +;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \ +;; RUN: | llvm-objdump -s - | FileCheck %s + +define i32 @foo (i32 %a, i32 %b) +{ + %1 = xor i32 %a, %b + ret i32 %1 +} + +; CHECK: 0000 004160f1 00c09f52
\ No newline at end of file |
