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-rw-r--r--llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td7
-rw-r--r--llvm/lib/Target/AArch64/SVEInstrFormats.td54
-rw-r--r--llvm/test/MC/AArch64/SVE/rdffr-diagnostics.s19
-rw-r--r--llvm/test/MC/AArch64/SVE/rdffr.s32
-rw-r--r--llvm/test/MC/AArch64/SVE/rdffrs-diagnostics.s30
-rw-r--r--llvm/test/MC/AArch64/SVE/rdffrs.s20
-rw-r--r--llvm/test/MC/AArch64/SVE/setffr.s14
-rw-r--r--llvm/test/MC/AArch64/SVE/wrffr-diagnostics.s19
-rw-r--r--llvm/test/MC/AArch64/SVE/wrffr.s20
9 files changed, 215 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index a3be890f874..7269e1e1983 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -12,6 +12,13 @@
//===----------------------------------------------------------------------===//
let Predicates = [HasSVE] in {
+
+ def RDFFR_PPz : sve_int_rdffr_pred<0b0, "rdffr">;
+ def RDFFRS_PPz : sve_int_rdffr_pred<0b1, "rdffrs">;
+ def RDFFR_P : sve_int_rdffr_unpred<"rdffr">;
+ def SETFFR : sve_int_setffr<"setffr">;
+ def WRFFR : sve_int_wrffr<"wrffr">;
+
defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">;
defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">;
defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">;
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 09e6f462a06..81687a0ba10 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -2092,6 +2092,60 @@ multiclass sve_int_perm_bin_perm_pp<bits<3> opc, string asm> {
def _D : sve_int_perm_bin_perm_pp<opc, 0b11, asm, PPR64>;
}
+class sve_int_rdffr_pred<bit s, string asm>
+: I<(outs PPR8:$Pd), (ins PPRAny:$Pg),
+ asm, "\t$Pd, $Pg/z",
+ "",
+ []>, Sched<[]> {
+ bits<4> Pd;
+ bits<4> Pg;
+ let Inst{31-23} = 0b001001010;
+ let Inst{22} = s;
+ let Inst{21-9} = 0b0110001111000;
+ let Inst{8-5} = Pg;
+ let Inst{4} = 0;
+ let Inst{3-0} = Pd;
+
+ let Defs = !if(!eq (s, 1), [NZCV], []);
+ let Uses = [FFR];
+}
+
+class sve_int_rdffr_unpred<string asm> : I<
+ (outs PPR8:$Pd), (ins),
+ asm, "\t$Pd",
+ "",
+ []>, Sched<[]> {
+ bits<4> Pd;
+ let Inst{31-4} = 0b0010010100011001111100000000;
+ let Inst{3-0} = Pd;
+
+ let Uses = [FFR];
+}
+
+class sve_int_wrffr<string asm>
+: I<(outs), (ins PPR8:$Pn),
+ asm, "\t$Pn",
+ "",
+ []>, Sched<[]> {
+ bits<4> Pn;
+ let Inst{31-9} = 0b00100101001010001001000;
+ let Inst{8-5} = Pn;
+ let Inst{4-0} = 0b00000;
+
+ let hasSideEffects = 1;
+ let Defs = [FFR];
+}
+
+class sve_int_setffr<string asm>
+: I<(outs), (ins),
+ asm, "",
+ "",
+ []>, Sched<[]> {
+ let Inst{31-0} = 0b00100101001011001001000000000000;
+
+ let hasSideEffects = 1;
+ let Defs = [FFR];
+}
//===----------------------------------------------------------------------===//
// SVE Permute Vector - Predicated Group
diff --git a/llvm/test/MC/AArch64/SVE/rdffr-diagnostics.s b/llvm/test/MC/AArch64/SVE/rdffr-diagnostics.s
new file mode 100644
index 00000000000..c5d80fee703
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/rdffr-diagnostics.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid element widths
+
+rdffr p0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: rdffr p0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+rdffr p0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: rdffr p0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+rdffr p0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: rdffr p0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/rdffr.s b/llvm/test/MC/AArch64/SVE/rdffr.s
new file mode 100644
index 00000000000..3ae4c69f95f
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/rdffr.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+rdffr p0.b
+// CHECK-INST: rdffr p0.b
+// CHECK-ENCODING: [0x00,0xf0,0x19,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 19 25 <unknown>
+
+rdffr p15.b
+// CHECK-INST: rdffr p15.b
+// CHECK-ENCODING: [0x0f,0xf0,0x19,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 0f f0 19 25 <unknown>
+
+rdffr p0.b, p0/z
+// CHECK-INST: rdffr p0.b, p0/z
+// CHECK-ENCODING: [0x00,0xf0,0x18,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 18 25 <unknown>
+
+rdffr p15.b, p15/z
+// CHECK-INST: rdffr p15.b, p15/z
+// CHECK-ENCODING: [0xef,0xf1,0x18,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef f1 18 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/rdffrs-diagnostics.s b/llvm/test/MC/AArch64/SVE/rdffrs-diagnostics.s
new file mode 100644
index 00000000000..615ccd514ef
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/rdffrs-diagnostics.s
@@ -0,0 +1,30 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// No unpredicated form
+
+rdffrs p0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: too few operands for instruction
+// CHECK: rdffrs p0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid element widths
+
+rdffrs p0.h, p0/z
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: rdffrs p0.h, p0/z
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+rdffrs p0.s, p0/z
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: rdffrs p0.s, p0/z
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+rdffrs p0.d, p0/z
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: rdffrs p0.d, p0/z
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
diff --git a/llvm/test/MC/AArch64/SVE/rdffrs.s b/llvm/test/MC/AArch64/SVE/rdffrs.s
new file mode 100644
index 00000000000..9586d84af94
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/rdffrs.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+rdffrs p0.b, p0/z
+// CHECK-INST: rdffrs p0.b, p0/z
+// CHECK-ENCODING: [0x00,0xf0,0x58,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 f0 58 25 <unknown>
+
+rdffrs p15.b, p15/z
+// CHECK-INST: rdffrs p15.b, p15/z
+// CHECK-ENCODING: [0xef,0xf1,0x58,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ef f1 58 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/setffr.s b/llvm/test/MC/AArch64/SVE/setffr.s
new file mode 100644
index 00000000000..17d5f178f30
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/setffr.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+setffr
+// CHECK-INST: setffr
+// CHECK-ENCODING: [0x00,0x90,0x2c,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 90 2c 25 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/wrffr-diagnostics.s b/llvm/test/MC/AArch64/SVE/wrffr-diagnostics.s
new file mode 100644
index 00000000000..822371b60d4
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/wrffr-diagnostics.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid element widths
+
+wrffr p0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: wrffr p0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+wrffr p0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: wrffr p0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+wrffr p0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register
+// CHECK: wrffr p0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/wrffr.s b/llvm/test/MC/AArch64/SVE/wrffr.s
new file mode 100644
index 00000000000..dec71605be8
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/wrffr.s
@@ -0,0 +1,20 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+wrffr p0.b
+// CHECK-INST: wrffr p0.b
+// CHECK-ENCODING: [0x00,0x90,0x28,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 90 28 25 <unknown>
+
+wrffr p15.b
+// CHECK-INST: wrffr p15.b
+// CHECK-ENCODING: [0xe0,0x91,0x28,0x25]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 91 28 25 <unknown>
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