diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 7 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/aggregate-align.ll | 6 |
2 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index a3ade981740..bc04f37331e 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -123,10 +123,9 @@ static std::string computeDataLayout(ARMSubtarget &ST) { else Ret += "-v128:64:128"; - // On thumb and APCS, only try to align aggregates to 32 bits (the default is - // 64 bits). - if (ST.isThumb() || ST.isAPCS_ABI()) - Ret += "-a:0:32"; + // Try to align aggregates to 32 bits (the default is 64 bits, which has no + // particular hardware support on 32-bit ARM). + Ret += "-a:0:32"; // Integer registers are 32 bits. Ret += "-n32"; diff --git a/llvm/test/CodeGen/ARM/aggregate-align.ll b/llvm/test/CodeGen/ARM/aggregate-align.ll new file mode 100644 index 00000000000..22fc57c1de7 --- /dev/null +++ b/llvm/test/CodeGen/ARM/aggregate-align.ll @@ -0,0 +1,6 @@ +; RUN: llc -mtriple=armv7-linux-gnueabi %s -o - | FileCheck %s + +@var = global {i8, i8} zeroinitializer + +; CHECK: .globl var +; CHECK-NEXT: .align 2 |
