diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCCallingConv.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/sjlj.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vrsave-spill.ll | 11 |
5 files changed, 18 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td index 2a680661d36..c8a29a3d2cf 100644 --- a/llvm/lib/Target/PowerPC/PPCCallingConv.td +++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td @@ -137,7 +137,8 @@ def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAV V20, V21, V22, V23, V24, V25, V26, V27, V28, V29, V30, V31)>; -def CSR_NoRegs : CalleeSavedRegs<(add)>; +def CSR_NoRegs : CalleeSavedRegs<(add VRSAVE)>; +def CSR_NoRegs_Darwin : CalleeSavedRegs<(add)>; def CSR_NoRegs_Altivec : CalleeSavedRegs<(add (sequence "V%u", 0, 31), VRSAVE)>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 2be8df9f988..1558856700c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -509,6 +509,8 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF, FrameIdx)); NonRI = true; } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { + assert(TM.getSubtargetImpl()->isDarwin() && + "VRSAVE only needs spill/restore on Darwin"); NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_VRSAVE)) .addReg(SrcReg, getKillRegState(isKill)), @@ -627,6 +629,8 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, FrameIdx)); NonRI = true; } else if (PPC::VRSAVERCRegClass.hasSubClassEq(RC)) { + assert(TM.getSubtargetImpl()->isDarwin() && + "VRSAVE only needs spill/restore on Darwin"); NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::RESTORE_VRSAVE), DestReg), diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index d5a307e2283..0ebf1e8a418 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -114,6 +114,8 @@ PPCRegisterInfo::getNoPreservedMask() const { if (!Subtarget.hasAltivec()) return CSR_NoRegs_Altivec_RegMask; + if (Subtarget.isDarwin()) + return CSR_NoRegs_Darwin_RegMask; return CSR_NoRegs_RegMask; } diff --git a/llvm/test/CodeGen/PowerPC/sjlj.ll b/llvm/test/CodeGen/PowerPC/sjlj.ll index 3440b314dd1..7ea35dafc3f 100644 --- a/llvm/test/CodeGen/PowerPC/sjlj.ll +++ b/llvm/test/CodeGen/PowerPC/sjlj.ll @@ -57,8 +57,12 @@ return: ; preds = %if.end, %if.then %3 = load i32* %retval ret i32 %3 +; FIXME: We should be saving VRSAVE on Darwin, but we're not! + ; CHECK: @main ; CHECK: std +; Make sure that we're not saving VRSAVE on non-Darwin: +; CHECK-NOT: mfspr ; CHECK: stfd ; CHECK: stvx diff --git a/llvm/test/CodeGen/PowerPC/vrsave-spill.ll b/llvm/test/CodeGen/PowerPC/vrsave-spill.ll index d4b07bc1f6e..c73206d8fc8 100644 --- a/llvm/test/CodeGen/PowerPC/vrsave-spill.ll +++ b/llvm/test/CodeGen/PowerPC/vrsave-spill.ll @@ -1,18 +1,19 @@ -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-apple-darwin -mcpu=g5 | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" -target triple = "powerpc64-unknown-linux-gnu" +target triple = "powerpc64-apple-darwin" define <4 x float> @foo(<4 x float> %a, <4 x float> %b) nounwind { entry: %c = fadd <4 x float> %a, %b + %d = fmul <4 x float> %c, %a call void asm sideeffect "", "~{VRsave}"() nounwind br label %return ; CHECK: @foo -; CHECK: mfspr {{[0-9]+}}, 256 -; CHECK: mtspr 256, {{[0-9]+}} +; CHECK: mfspr r{{[0-9]+}}, 256 +; CHECK: mtspr 256, r{{[0-9]+}} return: ; preds = %entry - ret <4 x float> %c + ret <4 x float> %d } |
