diff options
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstrInfo.td | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index 72b7d5088d9..7cec40c99e8 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -2008,13 +2008,12 @@ class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : let isCodeGenOnly = 1; } +// FIXME-GFX10: WIP. class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins, - string asm> : + string asm, int encodingFamily> : VINTRPCommon <outs, ins, asm, []>, VINTRPe <op>, - SIMCInstr<opName, SIEncodingFamily.SI> { - let AssemblerPredicate = SIAssemblerPredicate; - let DecoderNamespace = "GFX6GFX7"; + SIMCInstr<opName, encodingFamily> { let DisableDecoder = DisableSIDecoder; } @@ -2028,15 +2027,21 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins, let DisableDecoder = DisableVIDecoder; } +// FIXME-GFX10: WIP. multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern = []> { def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>; - def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>; + let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in { + def _si : VINTRP_Real_si <op, NAME, outs, ins, asm, SIEncodingFamily.SI>; + } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>; -} + let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in { + def _gfx10 : VINTRP_Real_si<op, NAME, outs, ins, asm, SIEncodingFamily.GFX10>; + } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" +} //===----------------------------------------------------------------------===// // Vector instruction mappings //===----------------------------------------------------------------------===// |
