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-rw-r--r--llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp35
-rw-r--r--llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp56
-rw-r--r--llvm/lib/Target/Hexagon/HexagonRegisterInfo.h3
3 files changed, 61 insertions, 33 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index d91b79dae86..4d6235a9fe5 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -125,7 +125,7 @@ using namespace llvm;
static cl::opt<bool> DisableDeallocRet("disable-hexagon-dealloc-ret",
cl::Hidden, cl::desc("Disable Dealloc Return for Hexagon target"));
-static cl::opt<int> NumberScavengerSlots("number-scavenger-slots",
+static cl::opt<unsigned> NumberScavengerSlots("number-scavenger-slots",
cl::Hidden, cl::desc("Set the number of scavenger slots"), cl::init(2),
cl::ZeroOrMore);
@@ -1121,11 +1121,10 @@ void HexagonFrameLowering::processFunctionBeforeFrameFinalized(
HMFI.setStackAlignBasePhysReg(AP);
}
-/// Returns true if there is no caller saved registers available.
+/// Returns true if there are no caller-saved registers available in class RC.
static bool needToReserveScavengingSpillSlots(MachineFunction &MF,
- const HexagonRegisterInfo &HRI) {
+ const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
MachineRegisterInfo &MRI = MF.getRegInfo();
- BitVector Reserved = HRI.getReservedRegs(MF);
auto IsUsed = [&HRI,&MRI] (unsigned Reg) -> bool {
for (MCRegAliasIterator AI(Reg, &HRI, true); AI.isValid(); ++AI)
@@ -1136,7 +1135,7 @@ static bool needToReserveScavengingSpillSlots(MachineFunction &MF,
// Check for an unused caller-saved register. Callee-saved registers
// have become pristine by now.
- for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF); *P; ++P)
+ for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P)
if (!IsUsed(*P))
return false;
@@ -1717,26 +1716,26 @@ void HexagonFrameLowering::determineCalleeSaves(MachineFunction &MF,
// We need to reserve a a spill slot if scavenging could potentially require
// spilling a scavenged register.
- if (!NewRegs.empty() && needToReserveScavengingSpillSlots(MF, HRI)) {
+ if (!NewRegs.empty()) {
+ MachineFrameInfo &MFI = *MF.getFrameInfo();
MachineRegisterInfo &MRI = MF.getRegInfo();
SetVector<const TargetRegisterClass*> SpillRCs;
+ // Reserve an int register in any case, because it could be used to hold
+ // the stack offset in case it does not fit into a spill instruction.
+ SpillRCs.insert(&Hexagon::IntRegsRegClass);
+
for (unsigned VR : NewRegs)
SpillRCs.insert(MRI.getRegClass(VR));
- MachineFrameInfo &MFI = *MF.getFrameInfo();
- const TargetRegisterClass &IntRC = Hexagon::IntRegsRegClass;
- if (SpillRCs.count(&IntRC)) {
- for (int i = 0; i < NumberScavengerSlots; i++) {
- int NewFI = MFI.CreateSpillStackObject(IntRC.getSize(),
- IntRC.getAlignment());
- RS->addScavengingFrameIndex(NewFI);
- }
- }
for (auto *RC : SpillRCs) {
- if (RC == &IntRC)
+ if (!needToReserveScavengingSpillSlots(MF, HRI, RC))
continue;
- int NewFI = MFI.CreateSpillStackObject(RC->getSize(), RC->getAlignment());
- RS->addScavengingFrameIndex(NewFI);
+ unsigned Num = RC == &Hexagon::IntRegsRegClass ? NumberScavengerSlots : 1;
+ unsigned S = RC->getSize(), A = RC->getAlignment();
+ for (unsigned i = 0; i < Num; i++) {
+ int NewFI = MFI.CreateSpillStackObject(S, A);
+ RS->addScavengingFrameIndex(NewFI);
+ }
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index 4e375719212..5d5b0a68529 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -53,23 +53,51 @@ bool HexagonRegisterInfo::isCalleeSaveReg(unsigned Reg) const {
const MCPhysReg *
-HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF) const {
- static const MCPhysReg CallerSavedRegsV4[] = {
- Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
- Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
- Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
- Hexagon::R15, 0
+HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF,
+ const TargetRegisterClass *RC) const {
+ using namespace Hexagon;
+
+ static const MCPhysReg Int32[] = {
+ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, 0
+ };
+ static const MCPhysReg Int64[] = {
+ D0, D1, D2, D3, D4, D5, D6, D7, 0
+ };
+ static const MCPhysReg Pred[] = {
+ P0, P1, P2, P3, 0
+ };
+ static const MCPhysReg VecSgl[] = {
+ V0, V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, V11, V12, V13,
+ V14, V15, V16, V17, V18, V19, V20, V21, V22, V23, V24, V25, V26, V27,
+ V28, V29, V30, V31, 0
+ };
+ static const MCPhysReg VecDbl[] = {
+ W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, 0
};
- switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
- case HexagonSubtarget::V4:
- case HexagonSubtarget::V5:
- case HexagonSubtarget::V55:
- case HexagonSubtarget::V60:
- return CallerSavedRegsV4;
+ switch (RC->getID()) {
+ case IntRegsRegClassID:
+ return Int32;
+ case DoubleRegsRegClassID:
+ return Int64;
+ case PredRegsRegClassID:
+ return Pred;
+ case VectorRegsRegClassID:
+ case VectorRegs128BRegClassID:
+ return VecSgl;
+ case VecDblRegsRegClassID:
+ case VecDblRegs128BRegClassID:
+ return VecDbl;
+ default:
+ break;
}
- llvm_unreachable(
- "Callee saved registers requested for unknown archtecture version");
+
+ static const MCPhysReg Empty[] = { 0 };
+#ifndef NDEBUG
+ dbgs() << "Register class: " << getRegClassName(RC) << "\n";
+#endif
+ llvm_unreachable("Unexpected register class");
+ return Empty;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
index e7eff1c0c57..fc70679bc93 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
@@ -61,7 +61,8 @@ public:
unsigned getFrameRegister() const;
unsigned getStackRegister() const;
- const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF) const;
+ const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF,
+ const TargetRegisterClass *RC) const;
unsigned getFirstCallerSavedNonParamReg() const;
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