diff options
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index b00e9966d7e..b5f709241f2 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -991,6 +991,11 @@ bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond) { // some registers, which would complicate the transformation considerably. if (!MS.isKill()) return false; + // Avoid predicating instructions that define a subregister. The code + // does not handle correctly cases where both subregisters of a register + // are defined by a condset. + if (MD.getSubReg()) + return false; RegisterRef RT(MS); unsigned PredR = MP.getReg(); |
