diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.h | 4 |
3 files changed, 13 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 0c7d386b0e9..8cf8f04bd66 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -517,7 +517,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, MaskAndBranchFoldingIsLegal = true; EnableExtLdPromotion = true; + // Set required alignment. setMinFunctionAlignment(2); + // Set preferred alignments. + setPrefFunctionAlignment(STI.getPrefFunctionAlignment()); + setPrefLoopAlignment(STI.getPrefLoopAlignment()); setHasExtractBitsInsn(true); diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 57957d1de53..3354cbd1a53 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -63,14 +63,17 @@ void AArch64Subtarget::initializeProperties() { case CortexA57: MaxInterleaveFactor = 4; break; + case ExynosM1: + PrefFunctionAlignment = 4; + PrefLoopAlignment = 3; + break; case Kryo: MaxInterleaveFactor = 4; VectorInsertExtractBaseCost = 2; break; - case Others: break; case CortexA35: break; case CortexA53: break; - case ExynosM1: break; + case Others: break; } } diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 6d26fa71c79..43d4141aadf 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -86,6 +86,8 @@ protected: uint16_t PrefetchDistance = 0; uint16_t MinPrefetchStride = 1; unsigned MaxPrefetchIterationsAhead = UINT_MAX; + unsigned PrefFunctionAlignment = 0; + unsigned PrefLoopAlignment = 0; // ReserveX18 - X18 is not available as a general purpose register. bool ReserveX18; @@ -195,6 +197,8 @@ public: unsigned getMaxPrefetchIterationsAhead() const { return MaxPrefetchIterationsAhead; } + unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; } + unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; } /// CPU has TBI (top byte of addresses is ignored during HW address /// translation) and OS enables it. |
