diff options
| -rw-r--r-- | llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 6 | ||||
| -rw-r--r-- | llvm/test/MC/X86/avx512-encodings.s | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 3d4bbafee66..a76eecaaee6 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -184,7 +184,7 @@ static bool isDisp8(int Value) { /// isCDisp8 - Return true if this signed displacement fits in a 8-bit /// compressed dispacement field. static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) { - assert(((TSFlags >> X86II::VEXShift) & X86II::EVEX) && + assert((TSFlags & X86II::EncodingMask) >> X86II::EncodingShift == X86II::EVEX && "Compressed 8-bit displacement is only valid for EVEX inst."); unsigned CD8E = (TSFlags >> X86II::EVEX_CD8EShift) & X86II::EVEX_CD8EMask; @@ -386,7 +386,9 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op, const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt); const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); unsigned BaseReg = Base.getReg(); - bool HasEVEX = (TSFlags >> X86II::VEXShift) & X86II::EVEX; + unsigned char Encoding = (TSFlags & X86II::EncodingMask) >> + X86II::EncodingShift; + bool HasEVEX = (Encoding == X86II::EVEX); // Handle %rip relative addressing. if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode diff --git a/llvm/test/MC/X86/avx512-encodings.s b/llvm/test/MC/X86/avx512-encodings.s index 38f9190d949..b2f1d11e081 100644 --- a/llvm/test/MC/X86/avx512-encodings.s +++ b/llvm/test/MC/X86/avx512-encodings.s @@ -43,3 +43,7 @@ vpbroadcastd %xmm0, %zmm1 {%k1} {z} // CHECK: vmovdqu64 {{.*}} {%k3} // CHECK: encoding: [0x62,0xf1,0xfe,0x4b,0x6f,0xc8] vmovdqu64 %zmm0, %zmm1 {%k3} + +// CHECK: vmovd +// CHECK: encoding: [0x62,0xe1,0x7d,0x08,0x7e,0xb4,0x24,0xac,0xff,0xff,0xff] +vmovd %xmm22, -84(%rsp)
\ No newline at end of file |
