diff options
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstructionSelector.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir | 29 |
2 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index c7ed3c3d6e3..dccd717eb99 100644 --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -299,6 +299,7 @@ bool ARMInstructionSelector::select(MachineInstr &I) const { break; } case G_ADD: + case G_GEP: I.setDesc(TII.get(ARM::ADDrr)); MIB.add(predOps(ARMCC::AL)).add(condCodeOp()); break; diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index 24b95647e95..847c10c2970 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -18,6 +18,8 @@ define void @test_stores() #0 { ret void } + define void @test_gep() { ret void } + define void @test_soft_fp_double() #0 { ret void } attributes #0 = { "target-features"="+vfp2,-neonfp" } @@ -437,6 +439,33 @@ body: | BX_RET 14, _ ... --- +name: test_gep +# CHECK-LABEL: name: test_gep +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } +# CHECK: id: [[PTR:[0-9]+]], class: gpr +# CHECK: id: [[OFF:[0-9]+]], class: gpr +# CHECK: id: [[GEP:[0-9]+]], class: gpr +body: | + bb.0: + liveins: %r0, %r1 + + %0(p0) = COPY %r0 + %1(s32) = COPY %r1 + + %2(p0) = G_GEP %0, %1(s32) + ; CHECK: %[[GEP]] = ADDrr %[[PTR]], %[[OFF]], 14, _, _ + + %r0 = COPY %2(p0) + BX_RET 14, _, implicit %r0 +... +--- name: test_soft_fp_double # CHECK-LABEL: name: test_soft_fp_double legalized: true |
