diff options
| -rw-r--r-- | llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 17 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86InstrAVX512.td | 42 | ||||
| -rw-r--r-- | llvm/test/MC/X86/AVX512F_SCALAR-64.s | 176 |
3 files changed, 115 insertions, 120 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 6786d69f9fe..fa079242e75 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -3013,6 +3013,23 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) { (MCID.TSFlags & X86II::EncodingMask) != X86II::VEX) return Match_Unsupported; + // These instructions match ambiguously with their VEX encoded counterparts + // and appear first in the matching table. Reject them unless we're forcing + // EVEX encoding. + // FIXME: We really need a way to break the ambiguity. + switch (Opc) { + case X86::VCVTSD2SIZrm_Int: + case X86::VCVTSD2SI64Zrm_Int: + case X86::VCVTSS2SIZrm_Int: + case X86::VCVTSS2SI64Zrm_Int: + case X86::VCVTTSD2SIZrm: case X86::VCVTTSD2SIZrm_Int: + case X86::VCVTTSD2SI64Zrm: case X86::VCVTTSD2SI64Zrm_Int: + case X86::VCVTTSS2SIZrm: case X86::VCVTTSS2SIZrm_Int: + case X86::VCVTTSS2SI64Zrm: case X86::VCVTTSS2SI64Zrm_Int: + if (ForcedVEXEncoding != VEXEncoding_EVEX) + return Match_Unsupported; + } + return Match_Success; } diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td index 28661b56bdf..a8158448151 100644 --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -7442,8 +7442,7 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT, X86VectorVTInfo DstVT, SDNode OpNode, SDNode OpNodeRnd, X86FoldableSchedWrite sched, string asm, - string aliasStr, - bit CodeGenOnly = 1> { + string aliasStr> { let Predicates = [HasAVX512] in { def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst), (ins SrcVT.RC:$src), !strconcat(asm,"\t{$src, $dst|$dst, $src}"), @@ -7454,7 +7453,6 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT, [(set DstVT.RC:$dst, (OpNodeRnd (SrcVT.VT SrcVT.RC:$src),(i32 timm:$rc)))]>, EVEX, VEX_LIG, EVEX_B, EVEX_RC, Sched<[sched]>; - let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in def rm_Int : SI<opc, MRMSrcMem, (outs DstVT.RC:$dst), (ins SrcVT.IntScalarMemOp:$src), !strconcat(asm,"\t{$src, $dst|$dst, $src}"), [(set DstVT.RC:$dst, (OpNode @@ -7466,14 +7464,6 @@ multiclass avx512_cvt_s_int_round<bits<8> opc, X86VectorVTInfo SrcVT, (!cast<Instruction>(NAME # "rr_Int") DstVT.RC:$dst, SrcVT.RC:$src), 0, "att">; def : InstAlias<"v" # asm # aliasStr # "\t{$rc, $src, $dst|$dst, $src, $rc}", (!cast<Instruction>(NAME # "rrb_Int") DstVT.RC:$dst, SrcVT.RC:$src, AVX512RC:$rc), 0, "att">; -} - -multiclass avx512_cvt_s_int_round_aliases<bits<8> opc, X86VectorVTInfo SrcVT, - X86VectorVTInfo DstVT, SDNode OpNode, - SDNode OpNodeRnd, - X86FoldableSchedWrite sched, string asm, - string aliasStr> : - avx512_cvt_s_int_round<opc, SrcVT, DstVT, OpNode, OpNodeRnd, sched, asm, aliasStr, 0> { def : InstAlias<"v" # asm # aliasStr # "\t{$src, $dst|$dst, $src}", (!cast<Instruction>(NAME # "rm_Int") DstVT.RC:$dst, SrcVT.IntScalarMemOp:$src), 0, "att">; @@ -7486,10 +7476,10 @@ defm VCVTSS2SIZ: avx512_cvt_s_int_round<0x2D, f32x_info, i32x_info,X86cvts2si, defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info, X86cvts2si, X86cvts2siRnd, WriteCvtSS2I, "cvtss2si", "{q}">, XS, VEX_W, EVEX_CD8<32, CD8VT1>; -defm VCVTSS2USIZ: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i32x_info, X86cvts2usi, +defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSS2I, "cvtss2usi", "{l}">, XS, EVEX_CD8<32, CD8VT1>; -defm VCVTSS2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f32x_info, i64x_info, X86cvts2usi, +defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSS2I, "cvtss2usi", "{q}">, XS, VEX_W, EVEX_CD8<32, CD8VT1>; defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info, X86cvts2si, @@ -7498,10 +7488,10 @@ defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info, X86cvts2si, defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info, X86cvts2si, X86cvts2siRnd, WriteCvtSD2I, "cvtsd2si", "{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>; -defm VCVTSD2USIZ: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i32x_info, X86cvts2usi, +defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSD2I, "cvtsd2usi", "{l}">, XD, EVEX_CD8<64, CD8VT1>; -defm VCVTSD2USI64Z: avx512_cvt_s_int_round_aliases<0x79, f64x_info, i64x_info, X86cvts2usi, +defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSD2I, "cvtsd2usi", "{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>; @@ -7593,8 +7583,7 @@ def : Pat<(v2f64 (X86Movsd multiclass avx512_cvt_s_all<bits<8> opc, string asm, X86VectorVTInfo _SrcRC, X86VectorVTInfo _DstRC, SDNode OpNode, SDNode OpNodeInt, SDNode OpNodeSAE, - X86FoldableSchedWrite sched, string aliasStr, - bit CodeGenOnly = 1>{ + X86FoldableSchedWrite sched, string aliasStr>{ let Predicates = [HasAVX512] in { let isCodeGenOnly = 1 in { def rr : AVX512<opc, MRMSrcReg, (outs _DstRC.RC:$dst), (ins _SrcRC.FRC:$src), @@ -7615,7 +7604,6 @@ let Predicates = [HasAVX512] in { !strconcat(asm,"\t{{sae}, $src, $dst|$dst, $src, {sae}}"), [(set _DstRC.RC:$dst, (OpNodeSAE (_SrcRC.VT _SrcRC.RC:$src)))]>, EVEX, VEX_LIG, EVEX_B, Sched<[sched]>; - let isCodeGenOnly = CodeGenOnly, ForceDisassemble = CodeGenOnly in def rm_Int : AVX512<opc, MRMSrcMem, (outs _DstRC.RC:$dst), (ins _SrcRC.IntScalarMemOp:$src), !strconcat(asm,"\t{$src, $dst|$dst, $src}"), @@ -7628,16 +7616,6 @@ let Predicates = [HasAVX512] in { (!cast<Instruction>(NAME # "rr_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0, "att">; def : InstAlias<asm # aliasStr # "\t{{sae}, $src, $dst|$dst, $src, {sae}}", (!cast<Instruction>(NAME # "rrb_Int") _DstRC.RC:$dst, _SrcRC.RC:$src), 0, "att">; -} - -multiclass avx512_cvt_s_all_unsigned<bits<8> opc, string asm, - X86VectorVTInfo _SrcRC, - X86VectorVTInfo _DstRC, SDNode OpNode, - SDNode OpNodeInt, SDNode OpNodeSAE, - X86FoldableSchedWrite sched, - string aliasStr> : - avx512_cvt_s_all<opc, asm, _SrcRC, _DstRC, OpNode, OpNodeInt, OpNodeSAE, sched, - aliasStr, 0> { def : InstAlias<asm # aliasStr # "\t{$src, $dst|$dst, $src}", (!cast<Instruction>(NAME # "rm_Int") _DstRC.RC:$dst, _SrcRC.IntScalarMemOp:$src), 0, "att">; @@ -7656,16 +7634,16 @@ defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i64x_info, fp_to_sint, X86cvtts2Int, X86cvtts2IntSAE, WriteCvtSD2I, "{q}">, VEX_W, XD, EVEX_CD8<64, CD8VT1>; -defm VCVTTSS2USIZ: avx512_cvt_s_all_unsigned<0x78, "vcvttss2usi", f32x_info, i32x_info, +defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i32x_info, fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSS2I, "{l}">, XS, EVEX_CD8<32, CD8VT1>; -defm VCVTTSS2USI64Z: avx512_cvt_s_all_unsigned<0x78, "vcvttss2usi", f32x_info, i64x_info, +defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i64x_info, fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSS2I, "{q}">, XS,VEX_W, EVEX_CD8<32, CD8VT1>; -defm VCVTTSD2USIZ: avx512_cvt_s_all_unsigned<0x78, "vcvttsd2usi", f64x_info, i32x_info, +defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i32x_info, fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSD2I, "{l}">, XD, EVEX_CD8<64, CD8VT1>; -defm VCVTTSD2USI64Z: avx512_cvt_s_all_unsigned<0x78, "vcvttsd2usi", f64x_info, i64x_info, +defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i64x_info, fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSD2I, "{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>; diff --git a/llvm/test/MC/X86/AVX512F_SCALAR-64.s b/llvm/test/MC/X86/AVX512F_SCALAR-64.s index b0b1fe5eb21..0b543539e7e 100644 --- a/llvm/test/MC/X86/AVX512F_SCALAR-64.s +++ b/llvm/test/MC/X86/AVX512F_SCALAR-64.s @@ -913,44 +913,44 @@ vcomiss %xmm15, %xmm15 vcomiss %xmm1, %xmm1 // CHECK: vcvtsd2si 485498096, %r13d -// CHECK: encoding: [0xc5,0x7b,0x2d,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvtsd2si 485498096, %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2d,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvtsd2si 485498096, %r13d // CHECK: vcvtsd2si 485498096, %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2d,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvtsd2si 485498096, %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2d,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvtsd2si 485498096, %r15 // CHECK: vcvtsd2si 512(%rdx), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2d,0xaa,0x00,0x02,0x00,0x00] -vcvtsd2si 512(%rdx), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2d,0x6a,0x40] +{evex} vcvtsd2si 512(%rdx), %r13d // CHECK: vcvtsd2si 512(%rdx), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2d,0xba,0x00,0x02,0x00,0x00] -vcvtsd2si 512(%rdx), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2d,0x7a,0x40] +{evex} vcvtsd2si 512(%rdx), %r15 // CHECK: vcvtsd2si 512(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2d,0xac,0x82,0x00,0x02,0x00,0x00] -vcvtsd2si 512(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2d,0x6c,0x82,0x40] +{evex} vcvtsd2si 512(%rdx,%rax,4), %r13d // CHECK: vcvtsd2si -512(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2d,0xac,0x82,0x00,0xfe,0xff,0xff] -vcvtsd2si -512(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2d,0x6c,0x82,0xc0] +{evex} vcvtsd2si -512(%rdx,%rax,4), %r13d // CHECK: vcvtsd2si 512(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2d,0xbc,0x82,0x00,0x02,0x00,0x00] -vcvtsd2si 512(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2d,0x7c,0x82,0x40] +{evex} vcvtsd2si 512(%rdx,%rax,4), %r15 // CHECK: vcvtsd2si -512(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2d,0xbc,0x82,0x00,0xfe,0xff,0xff] -vcvtsd2si -512(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2d,0x7c,0x82,0xc0] +{evex} vcvtsd2si -512(%rdx,%rax,4), %r15 // CHECK: vcvtsd2si 512(%rdx,%rax), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2d,0xac,0x02,0x00,0x02,0x00,0x00] -vcvtsd2si 512(%rdx,%rax), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2d,0x6c,0x02,0x40] +{evex} vcvtsd2si 512(%rdx,%rax), %r13d // CHECK: vcvtsd2si 512(%rdx,%rax), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2d,0xbc,0x02,0x00,0x02,0x00,0x00] -vcvtsd2si 512(%rdx,%rax), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2d,0x7c,0x02,0x40] +{evex} vcvtsd2si 512(%rdx,%rax), %r15 // CHECK: vcvtsd2si {rd-sae}, %xmm15, %r13d // CHECK: encoding: [0x62,0x51,0x7f,0x38,0x2d,0xef] @@ -1945,44 +1945,44 @@ vcvtss2sd %xmm1, %xmm1, %xmm1 {%k2} vcvtss2sd %xmm1, %xmm1, %xmm1 {%k2} {z} // CHECK: vcvtss2si 256(%rdx), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2d,0xaa,0x00,0x01,0x00,0x00] -vcvtss2si 256(%rdx), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2d,0x6a,0x40] +{evex} {evex} vcvtss2si 256(%rdx), %r13d // CHECK: vcvtss2si 256(%rdx), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0xba,0x00,0x01,0x00,0x00] -vcvtss2si 256(%rdx), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2d,0x7a,0x40] +{evex} vcvtss2si 256(%rdx), %r15 // CHECK: vcvtss2si 256(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2d,0xac,0x82,0x00,0x01,0x00,0x00] -vcvtss2si 256(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2d,0x6c,0x82,0x40] +{evex} vcvtss2si 256(%rdx,%rax,4), %r13d // CHECK: vcvtss2si -256(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2d,0xac,0x82,0x00,0xff,0xff,0xff] -vcvtss2si -256(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2d,0x6c,0x82,0xc0] +{evex} vcvtss2si -256(%rdx,%rax,4), %r13d // CHECK: vcvtss2si 256(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0xbc,0x82,0x00,0x01,0x00,0x00] -vcvtss2si 256(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2d,0x7c,0x82,0x40] +{evex} vcvtss2si 256(%rdx,%rax,4), %r15 // CHECK: vcvtss2si -256(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0xbc,0x82,0x00,0xff,0xff,0xff] -vcvtss2si -256(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2d,0x7c,0x82,0xc0] +{evex} vcvtss2si -256(%rdx,%rax,4), %r15 // CHECK: vcvtss2si 256(%rdx,%rax), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2d,0xac,0x02,0x00,0x01,0x00,0x00] -vcvtss2si 256(%rdx,%rax), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2d,0x6c,0x02,0x40] +{evex} vcvtss2si 256(%rdx,%rax), %r13d // CHECK: vcvtss2si 256(%rdx,%rax), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0xbc,0x02,0x00,0x01,0x00,0x00] -vcvtss2si 256(%rdx,%rax), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2d,0x7c,0x02,0x40] +{evex} vcvtss2si 256(%rdx,%rax), %r15 // CHECK: vcvtss2si 485498096, %r13d -// CHECK: encoding: [0xc5,0x7a,0x2d,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvtss2si 485498096, %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2d,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvtss2si 485498096, %r13d // CHECK: vcvtss2si 485498096, %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvtss2si 485498096, %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2d,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvtss2si 485498096, %r15 // CHECK: vcvtss2si {rd-sae}, %xmm15, %r13d // CHECK: encoding: [0x62,0x51,0x7e,0x38,0x2d,0xef] @@ -2201,52 +2201,52 @@ vcvtss2usi %xmm1, %r13d vcvtss2usi %xmm1, %r15 // CHECK: vcvttsd2si 485498096, %r13d -// CHECK: encoding: [0xc5,0x7b,0x2c,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvttsd2si 485498096, %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2c,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvttsd2si 485498096, %r13d // CHECK: vcvttsd2si 485498096, %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2c,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvttsd2si 485498096, %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2c,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvttsd2si 485498096, %r15 // CHECK: vcvttsd2si 512(%rdx), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2c,0xaa,0x00,0x02,0x00,0x00] -vcvttsd2si 512(%rdx), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2c,0x6a,0x40] +{evex} vcvttsd2si 512(%rdx), %r13d // CHECK: vcvttsd2si 512(%rdx), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2c,0xba,0x00,0x02,0x00,0x00] -vcvttsd2si 512(%rdx), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2c,0x7a,0x40] +{evex} vcvttsd2si 512(%rdx), %r15 // CHECK: vcvttsd2si 512(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2c,0xac,0x82,0x00,0x02,0x00,0x00] -vcvttsd2si 512(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2c,0x6c,0x82,0x40] +{evex} vcvttsd2si 512(%rdx,%rax,4), %r13d // CHECK: vcvttsd2si -512(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2c,0xac,0x82,0x00,0xfe,0xff,0xff] -vcvttsd2si -512(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2c,0x6c,0x82,0xc0] +{evex} vcvttsd2si -512(%rdx,%rax,4), %r13d // CHECK: vcvttsd2si 512(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2c,0xbc,0x82,0x00,0x02,0x00,0x00] -vcvttsd2si 512(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2c,0x7c,0x82,0x40] +{evex} vcvttsd2si 512(%rdx,%rax,4), %r15 // CHECK: vcvttsd2si -512(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2c,0xbc,0x82,0x00,0xfe,0xff,0xff] -vcvttsd2si -512(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2c,0x7c,0x82,0xc0] +{evex} vcvttsd2si -512(%rdx,%rax,4), %r15 // CHECK: vcvttsd2si 512(%rdx,%rax), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2c,0xac,0x02,0x00,0x02,0x00,0x00] -vcvttsd2si 512(%rdx,%rax), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2c,0x6c,0x02,0x40] +{evex} vcvttsd2si 512(%rdx,%rax), %r13d // CHECK: vcvttsd2si 512(%rdx,%rax), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2c,0xbc,0x02,0x00,0x02,0x00,0x00] -vcvttsd2si 512(%rdx,%rax), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2c,0x7c,0x02,0x40] +{evex} vcvttsd2si 512(%rdx,%rax), %r15 // CHECK: vcvttsd2si (%rdx), %r13d -// CHECK: encoding: [0xc5,0x7b,0x2c,0x2a] -vcvttsd2si (%rdx), %r13d +// CHECK: encoding: [0x62,0x71,0x7f,0x08,0x2c,0x2a] +{evex} vcvttsd2si (%rdx), %r13d // CHECK: vcvttsd2si (%rdx), %r15 -// CHECK: encoding: [0xc4,0x61,0xfb,0x2c,0x3a] -vcvttsd2si (%rdx), %r15 +// CHECK: encoding: [0x62,0x71,0xff,0x08,0x2c,0x3a] +{evex} vcvttsd2si (%rdx), %r15 // CHECK: vcvttsd2si {sae}, %xmm15, %r13d // CHECK: encoding: [0x62,0x51,0x7f,0x18,0x2c,0xef] @@ -2361,52 +2361,52 @@ vcvttsd2usi %xmm1, %r13d vcvttsd2usi %xmm1, %r15 // CHECK: vcvttss2si 256(%rdx), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2c,0xaa,0x00,0x01,0x00,0x00] -vcvttss2si 256(%rdx), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2c,0x6a,0x40] +{evex} vcvttss2si 256(%rdx), %r13d // CHECK: vcvttss2si 256(%rdx), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2c,0xba,0x00,0x01,0x00,0x00] -vcvttss2si 256(%rdx), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2c,0x7a,0x40] +{evex} vcvttss2si 256(%rdx), %r15 // CHECK: vcvttss2si 256(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2c,0xac,0x82,0x00,0x01,0x00,0x00] -vcvttss2si 256(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2c,0x6c,0x82,0x40] +{evex} vcvttss2si 256(%rdx,%rax,4), %r13d // CHECK: vcvttss2si -256(%rdx,%rax,4), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2c,0xac,0x82,0x00,0xff,0xff,0xff] -vcvttss2si -256(%rdx,%rax,4), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2c,0x6c,0x82,0xc0] +{evex} vcvttss2si -256(%rdx,%rax,4), %r13d // CHECK: vcvttss2si 256(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2c,0xbc,0x82,0x00,0x01,0x00,0x00] -vcvttss2si 256(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2c,0x7c,0x82,0x40] +{evex} vcvttss2si 256(%rdx,%rax,4), %r15 // CHECK: vcvttss2si -256(%rdx,%rax,4), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2c,0xbc,0x82,0x00,0xff,0xff,0xff] -vcvttss2si -256(%rdx,%rax,4), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2c,0x7c,0x82,0xc0] +{evex} vcvttss2si -256(%rdx,%rax,4), %r15 // CHECK: vcvttss2si 256(%rdx,%rax), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2c,0xac,0x02,0x00,0x01,0x00,0x00] -vcvttss2si 256(%rdx,%rax), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2c,0x6c,0x02,0x40] +{evex} vcvttss2si 256(%rdx,%rax), %r13d // CHECK: vcvttss2si 256(%rdx,%rax), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2c,0xbc,0x02,0x00,0x01,0x00,0x00] -vcvttss2si 256(%rdx,%rax), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2c,0x7c,0x02,0x40] +{evex} vcvttss2si 256(%rdx,%rax), %r15 // CHECK: vcvttss2si 485498096, %r13d -// CHECK: encoding: [0xc5,0x7a,0x2c,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvttss2si 485498096, %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2c,0x2c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvttss2si 485498096, %r13d // CHECK: vcvttss2si 485498096, %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2c,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] -vcvttss2si 485498096, %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2c,0x3c,0x25,0xf0,0x1c,0xf0,0x1c] +{evex} vcvttss2si 485498096, %r15 // CHECK: vcvttss2si (%rdx), %r13d -// CHECK: encoding: [0xc5,0x7a,0x2c,0x2a] -vcvttss2si (%rdx), %r13d +// CHECK: encoding: [0x62,0x71,0x7e,0x08,0x2c,0x2a] +{evex} vcvttss2si (%rdx), %r13d // CHECK: vcvttss2si (%rdx), %r15 -// CHECK: encoding: [0xc4,0x61,0xfa,0x2c,0x3a] -vcvttss2si (%rdx), %r15 +// CHECK: encoding: [0x62,0x71,0xfe,0x08,0x2c,0x3a] +{evex} vcvttss2si (%rdx), %r15 // CHECK: vcvttss2si {sae}, %xmm15, %r13d // CHECK: encoding: [0x62,0x51,0x7e,0x18,0x2c,0xef] |
