diff options
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/ldst-opt.mir | 19 |
2 files changed, 26 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index c45c0b4c8ed..005f2d51e40 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -808,7 +808,13 @@ AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI, // Remove the load, if the destination register of the loads is the same // register for stored value. if (StRt == LdRt && LoadSize == 8) { - StoreI->clearRegisterKills(StRt, TRI); + for (MachineInstr &MI : make_range(StoreI->getIterator(), + LoadI->getIterator())) { + if (MI.killsRegister(StRt, TRI)) { + MI.clearRegisterKills(StRt, TRI); + break; + } + } DEBUG(dbgs() << "Remove load instruction:\n "); DEBUG(LoadI->print(dbgs())); DEBUG(dbgs() << "\n"); diff --git a/llvm/test/CodeGen/AArch64/ldst-opt.mir b/llvm/test/CodeGen/AArch64/ldst-opt.mir index 5b3576d898e..9cb9528cc62 100644 --- a/llvm/test/CodeGen/AArch64/ldst-opt.mir +++ b/llvm/test/CodeGen/AArch64/ldst-opt.mir @@ -162,3 +162,22 @@ body: | # CHECK: UBFMWri undef %w1 # CHECK: STRHHui undef %w3 # CHECK: ANDWri undef %w3 +--- +name: promote-load-from-store-trivial-kills +tracksRegLiveness: true +body: | + bb.0: + liveins: %x0, %lr + + STRXui %x0, %sp, 0 :: (store 8) + STRXui killed %x0, %sp, 2 :: (store 8) + %x0 = LDRXui %sp, 0 :: (load 8) + BL $bar, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit-def %sp + RET %lr +... +# CHECK-LABEL: name: promote-load-from-store-trivial-kills +# CHECK: STRXui %x0, %sp, 0 +# CHECK: STRXui %x0, %sp, 2 +# CHECK-NOT: LDRXui +# CHECK-NOT: ORR +# CHECK: BL $bar, csr_aarch64_aapcs, implicit-def %lr, implicit %sp, implicit %x0, implicit-def %sp |
