diff options
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir index 0b056e86496..e5eadf66e1f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -21,6 +21,10 @@ entry: ret void } + define void @defaultMappingDefRepair() { + entry: + ret void + } ... --- @@ -100,3 +104,27 @@ body: | %0(32) = COPY %s0 %1(32) = G_ADD i32 %0, %0 ... + +--- +# Check that we repair the definition of %1. +# %1 is forced to be into FPR, but its definition actually +# requires that it lives in GPR. Make sure regbankselect +# fixes that. +name: defaultMappingDefRepair +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: fpr } +# CHECK-NEXT: - { id: 2, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: fpr } +body: | + bb.0.entry: + liveins: %w0 + ; CHECK: %0(32) = COPY %w0 + ; CHECK-NEXT: %2(32) = G_ADD i32 %0, %w0 + ; CHECK-NEXT: %1(32) = COPY %2 + %0(32) = COPY %w0 + %1(32) = G_ADD i32 %0, %w0 +... |
