diff options
| -rw-r--r-- | llvm/include/llvm/Target/TargetLowering.h | 12 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 | 
2 files changed, 17 insertions, 3 deletions
diff --git a/llvm/include/llvm/Target/TargetLowering.h b/llvm/include/llvm/Target/TargetLowering.h index 08420ef70b9..153138f08af 100644 --- a/llvm/include/llvm/Target/TargetLowering.h +++ b/llvm/include/llvm/Target/TargetLowering.h @@ -1600,6 +1600,18 @@ public:      return false;    } +  /// isFNegFree - Return true if an fneg operation is free to the point where +  /// it is never worthwhile to replace it with a bitwise operation. +  virtual bool isFNegFree(EVT) const { +    return false; +  } + +  /// isFAbsFree - Return true if an fneg operation is free to the point where +  /// it is never worthwhile to replace it with a bitwise operation. +  virtual bool isFAbsFree(EVT) const { +    return false; +  } +    /// isNarrowingProfitable - Return true if it's profitable to narrow    /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow    /// from i32 to i8 but not from i32 to i16. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 08946070b44..a71cf82cd58 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5342,7 +5342,8 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {    // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)    // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))    // This often reduces constant pool loads. -  if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && +  if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || +       (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) &&        N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {      SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,                                    N0.getOperand(0)); @@ -5993,7 +5994,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) {    // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading    // constant pool values. -  if (N0.getOpcode() == ISD::BITCAST && +  if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&        !VT.isVector() &&        N0.getNode()->hasOneUse() &&        N0.getOperand(0).getValueType().isInteger()) { @@ -6029,7 +6030,8 @@ SDValue DAGCombiner::visitFABS(SDNode *N) {    // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading    // constant pool values. -  if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && +  if (!TLI.isFAbsFree(VT) &&  +      N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&        N0.getOperand(0).getValueType().isInteger() &&        !N0.getOperand(0).getValueType().isVector()) {      SDValue Int = N0.getOperand(0);  | 

