diff options
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 16 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 1 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/ppc32-pic.ll | 4 |
4 files changed, 23 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index a81131b3adc..1dd1e4d3d24 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -644,6 +644,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { .addImm(FPOffset) .addReg(SPReg); + if (isPIC && !isDarwinABI && !isPPC64 && + MF.getInfo<PPCFunctionInfo>()->usesPICBase()) + // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. + BuildMI(MBB, MBBI, dl, StoreInst) + .addReg(PPC::R30) + .addImm(-8U) + .addReg(SPReg); + if (HasBP) // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. BuildMI(MBB, MBBI, dl, StoreInst) @@ -1003,6 +1011,14 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF, .addImm(FPOffset) .addReg(SPReg); + if (isPIC && !isDarwinABI && !isPPC64 && + MF.getInfo<PPCFunctionInfo>()->usesPICBase()) + // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. + BuildMI(MBB, MBBI, dl, LoadInst) + .addReg(PPC::R30) + .addImm(-8U) + .addReg(SPReg); + if (HasBP) BuildMI(MBB, MBBI, dl, LoadInst, BPReg) .addImm(BPOffset) diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 6aa786f1173..75ab3430b49 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -307,6 +307,7 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { if (M->getPICLevel() == PICLevel::Small) { BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); + MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true); } else { BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); diff --git a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll index 3ee1cef2bb0..ac638dfec09 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-pic-large.ll @@ -12,12 +12,14 @@ entry: ; LARGE-BSS: [[POFF:\.L[0-9]+\$poff]]: ; LARGE-BSS-NEXT: .long .LTOC-[[PB:\.L[0-9]+\$pb]] ; LARGE-BSS-NEXT: foo: +; LARGE-BSS: stw 30, -8(1) ; LARGE-BSS: bl [[PB]] ; LARGE-BSS-NEXT: [[PB]]: ; LARGE-BSS: mflr 30 ; LARGE-BSS: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30) ; LARGE-BSS-NEXT: add 30, [[REG]], 30 ; LARGE-BSS: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30) -; LARGE-BSS: lwz {{[0-9]+}}, 0([[VREG]]) +; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]]) +; LARGE-BSS-DAG: lwz 30, -8(1) ; LARGE-BSS: [[VREF]]: ; LARGE-BSS-NEXT: .long bar diff --git a/llvm/test/CodeGen/PowerPC/ppc32-pic.ll b/llvm/test/CodeGen/PowerPC/ppc32-pic.ll index 6c0d9890e86..0ea50824579 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-pic.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-pic.ll @@ -10,7 +10,9 @@ entry: !llvm.module.flags = !{!0} !0 = !{i32 1, !"PIC Level", i32 1} ; SMALL-BSS-LABEL:foo: +; SMALL-BSS: stw 30, -8(1) ; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4 ; SMALL-BSS: mflr 30 ; SMALL-BSS: lwz [[VREG:[0-9]+]], bar@GOT(30) -; SMALL-BSS: lwz {{[0-9]+}}, 0([[VREG]]) +; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]]) +; SMALL-BSS-DAG: lwz 30, -8(1) |
