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-rw-r--r--llvm/lib/Target/Hexagon/BitTracker.cpp84
-rw-r--r--llvm/lib/Target/Hexagon/BitTracker.h10
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp9
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitTracker.cpp77
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitTracker.h8
-rw-r--r--llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp28
-rw-r--r--llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp168
-rw-r--r--llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp132
-rw-r--r--llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp12
-rw-r--r--llvm/lib/Target/Hexagon/HexagonGenMux.cpp12
-rw-r--r--llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp13
-rw-r--r--llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp136
-rw-r--r--llvm/lib/Target/Hexagon/HexagonPeephole.cpp94
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp53
-rw-r--r--llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp32
15 files changed, 426 insertions, 442 deletions
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 724c9b60898..d052a835fbd 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -733,18 +733,18 @@ BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const {
return BitMask(0, W-1);
}
-
-bool BT::MachineEvaluator::evaluate(const MachineInstr *MI,
- const CellMapType &Inputs, CellMapType &Outputs) const {
- unsigned Opc = MI->getOpcode();
+bool BT::MachineEvaluator::evaluate(const MachineInstr &MI,
+ const CellMapType &Inputs,
+ CellMapType &Outputs) const {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case TargetOpcode::REG_SEQUENCE: {
- RegisterRef RD = MI->getOperand(0);
+ RegisterRef RD = MI.getOperand(0);
assert(RD.Sub == 0);
- RegisterRef RS = MI->getOperand(1);
- unsigned SS = MI->getOperand(2).getImm();
- RegisterRef RT = MI->getOperand(3);
- unsigned ST = MI->getOperand(4).getImm();
+ RegisterRef RS = MI.getOperand(1);
+ unsigned SS = MI.getOperand(2).getImm();
+ RegisterRef RT = MI.getOperand(3);
+ unsigned ST = MI.getOperand(4).getImm();
assert(SS != ST);
uint16_t W = getRegBitWidth(RD);
@@ -758,8 +758,8 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr *MI,
case TargetOpcode::COPY: {
// COPY can transfer a smaller register into a wider one.
// If that is the case, fill the remaining high bits with 0.
- RegisterRef RD = MI->getOperand(0);
- RegisterRef RS = MI->getOperand(1);
+ RegisterRef RD = MI.getOperand(0);
+ RegisterRef RS = MI.getOperand(1);
assert(RD.Sub == 0);
uint16_t WD = getRegBitWidth(RD);
uint16_t WS = getRegBitWidth(RS);
@@ -782,12 +782,12 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr *MI,
// Main W-Z implementation.
-void BT::visitPHI(const MachineInstr *PI) {
- int ThisN = PI->getParent()->getNumber();
+void BT::visitPHI(const MachineInstr &PI) {
+ int ThisN = PI.getParent()->getNumber();
if (Trace)
- dbgs() << "Visit FI(BB#" << ThisN << "): " << *PI;
+ dbgs() << "Visit FI(BB#" << ThisN << "): " << PI;
- const MachineOperand &MD = PI->getOperand(0);
+ const MachineOperand &MD = PI.getOperand(0);
assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");
RegisterRef DefRR(MD);
uint16_t DefBW = ME.getRegBitWidth(DefRR);
@@ -798,8 +798,8 @@ void BT::visitPHI(const MachineInstr *PI) {
bool Changed = false;
- for (unsigned i = 1, n = PI->getNumOperands(); i < n; i += 2) {
- const MachineBasicBlock *PB = PI->getOperand(i+1).getMBB();
+ for (unsigned i = 1, n = PI.getNumOperands(); i < n; i += 2) {
+ const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB();
int PredN = PB->getNumber();
if (Trace)
dbgs() << " edge BB#" << PredN << "->BB#" << ThisN;
@@ -809,7 +809,7 @@ void BT::visitPHI(const MachineInstr *PI) {
continue;
}
- RegisterRef RU = PI->getOperand(i);
+ RegisterRef RU = PI.getOperand(i);
RegisterCell ResC = ME.getCell(RU, Map);
if (Trace)
dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
@@ -826,22 +826,21 @@ void BT::visitPHI(const MachineInstr *PI) {
}
}
-
-void BT::visitNonBranch(const MachineInstr *MI) {
+void BT::visitNonBranch(const MachineInstr &MI) {
if (Trace) {
- int ThisN = MI->getParent()->getNumber();
- dbgs() << "Visit MI(BB#" << ThisN << "): " << *MI;
+ int ThisN = MI.getParent()->getNumber();
+ dbgs() << "Visit MI(BB#" << ThisN << "): " << MI;
}
- if (MI->isDebugValue())
+ if (MI.isDebugValue())
return;
- assert(!MI->isBranch() && "Unexpected branch instruction");
+ assert(!MI.isBranch() && "Unexpected branch instruction");
CellMapType ResMap;
bool Eval = ME.evaluate(MI, Map, ResMap);
if (Trace && Eval) {
- for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isUse())
continue;
RegisterRef RU(MO);
@@ -859,8 +858,8 @@ void BT::visitNonBranch(const MachineInstr *MI) {
// Iterate over all definitions of the instruction, and update the
// cells accordingly.
- for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
// Visit register defs only.
if (!MO.isReg() || !MO.isDef())
continue;
@@ -907,9 +906,8 @@ void BT::visitNonBranch(const MachineInstr *MI) {
}
}
-
-void BT::visitBranchesFrom(const MachineInstr *BI) {
- const MachineBasicBlock &B = *BI->getParent();
+void BT::visitBranchesFrom(const MachineInstr &BI) {
+ const MachineBasicBlock &B = *BI.getParent();
MachineBasicBlock::const_iterator It = BI, End = B.end();
BranchTargetList Targets, BTs;
bool FallsThrough = true, DefaultToAll = false;
@@ -917,11 +915,11 @@ void BT::visitBranchesFrom(const MachineInstr *BI) {
do {
BTs.clear();
- const MachineInstr *MI = &*It;
+ const MachineInstr &MI = *It;
if (Trace)
- dbgs() << "Visit BR(BB#" << ThisN << "): " << *MI;
- assert(MI->isBranch() && "Expecting branch instruction");
- InstrExec.insert(MI);
+ dbgs() << "Visit BR(BB#" << ThisN << "): " << MI;
+ assert(MI.isBranch() && "Expecting branch instruction");
+ InstrExec.insert(&MI);
bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough);
if (!Eval) {
// If the evaluation failed, we will add all targets. Keep going in
@@ -985,11 +983,11 @@ void BT::visitUsesOf(unsigned Reg) {
if (!InstrExec.count(UseI))
continue;
if (UseI->isPHI())
- visitPHI(UseI);
+ visitPHI(*UseI);
else if (!UseI->isBranch())
- visitNonBranch(UseI);
+ visitNonBranch(*UseI);
else
- visitBranchesFrom(UseI);
+ visitBranchesFrom(*UseI);
}
}
@@ -1086,8 +1084,8 @@ void BT::run() {
MachineBasicBlock::const_iterator It = B.begin(), End = B.end();
// Visit PHI nodes first.
while (It != End && It->isPHI()) {
- const MachineInstr *PI = &*It++;
- InstrExec.insert(PI);
+ const MachineInstr &PI = *It++;
+ InstrExec.insert(&PI);
visitPHI(PI);
}
@@ -1100,8 +1098,8 @@ void BT::run() {
// Visit non-branch instructions.
while (It != End && !It->isBranch()) {
- const MachineInstr *MI = &*It++;
- InstrExec.insert(MI);
+ const MachineInstr &MI = *It++;
+ InstrExec.insert(&MI);
visitNonBranch(MI);
}
// If block end has been reached, add the fall-through edge to the queue.
@@ -1116,7 +1114,7 @@ void BT::run() {
} else {
// Handle the remaining sequence of branches. This function will update
// the work queue.
- visitBranchesFrom(It);
+ visitBranchesFrom(*It);
}
} // while (!FlowQ->empty())
diff --git a/llvm/lib/Target/Hexagon/BitTracker.h b/llvm/lib/Target/Hexagon/BitTracker.h
index 959c8318fd6..5b925fe696f 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.h
+++ b/llvm/lib/Target/Hexagon/BitTracker.h
@@ -51,9 +51,9 @@ struct BitTracker {
bool reached(const MachineBasicBlock *B) const;
private:
- void visitPHI(const MachineInstr *PI);
- void visitNonBranch(const MachineInstr *MI);
- void visitBranchesFrom(const MachineInstr *BI);
+ void visitPHI(const MachineInstr &PI);
+ void visitNonBranch(const MachineInstr &MI);
+ void visitBranchesFrom(const MachineInstr &BI);
void visitUsesOf(unsigned Reg);
void reset();
@@ -417,13 +417,13 @@ struct BitTracker::MachineEvaluator {
// Evaluate a non-branching machine instruction, given the cell map with
// the input values. Place the results in the Outputs map. Return "true"
// if evaluation succeeded, "false" otherwise.
- virtual bool evaluate(const MachineInstr *MI, const CellMapType &Inputs,
+ virtual bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
CellMapType &Outputs) const;
// Evaluate a branch, given the cell map with the input values. Fill out
// a list of all possible branch targets and indicate (through a flag)
// whether the branch could fall-through. Return "true" if this information
// has been successfully computed, "false" otherwise.
- virtual bool evaluate(const MachineInstr *BI, const CellMapType &Inputs,
+ virtual bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
BranchTargetList &Targets, bool &FallsThru) const = 0;
const TargetRegisterInfo &TRI;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 93dd6f8f080..c8b4a4cf938 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1318,7 +1318,7 @@ namespace {
: Transformation(true), HII(hii), MRI(mri), BT(bt) {}
bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
private:
- bool isTfrConst(const MachineInstr *MI) const;
+ bool isTfrConst(const MachineInstr &MI) const;
bool isConst(unsigned R, int64_t &V) const;
unsigned genTfrConst(const TargetRegisterClass *RC, int64_t C,
MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL);
@@ -1346,9 +1346,8 @@ bool ConstGeneration::isConst(unsigned R, int64_t &C) const {
return true;
}
-
-bool ConstGeneration::isTfrConst(const MachineInstr *MI) const {
- unsigned Opc = MI->getOpcode();
+bool ConstGeneration::isTfrConst(const MachineInstr &MI) const {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::A2_combineii:
case Hexagon::A4_combineii:
@@ -1418,7 +1417,7 @@ bool ConstGeneration::processBlock(MachineBasicBlock &B, const RegisterSet&) {
RegisterSet Defs;
for (auto I = B.begin(), E = B.end(); I != E; ++I) {
- if (isTfrConst(I))
+ if (isTfrConst(*I))
continue;
Defs.clear();
HBS::getInstrDefs(*I, Defs);
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 21eff079c99..78b57d27ad5 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -102,9 +102,9 @@ class RegisterRefs {
std::vector<BT::RegisterRef> Vector;
public:
- RegisterRefs(const MachineInstr *MI) : Vector(MI->getNumOperands()) {
+ RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) {
for (unsigned i = 0, n = Vector.size(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ const MachineOperand &MO = MI.getOperand(i);
if (MO.isReg())
Vector[i] = BT::RegisterRef(MO);
// For indices that don't correspond to registers, the entry will
@@ -121,13 +121,14 @@ public:
};
}
-bool HexagonEvaluator::evaluate(const MachineInstr *MI,
- const CellMapType &Inputs, CellMapType &Outputs) const {
+bool HexagonEvaluator::evaluate(const MachineInstr &MI,
+ const CellMapType &Inputs,
+ CellMapType &Outputs) const {
unsigned NumDefs = 0;
// Sanity verification: there should not be any defs with subregisters.
- for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef())
continue;
NumDefs++;
@@ -137,7 +138,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr *MI,
if (NumDefs == 0)
return false;
- if (MI->mayLoad())
+ if (MI.mayLoad())
return evaluateLoad(MI, Inputs, Outputs);
// Check COPY instructions that copy formal parameters into virtual
@@ -154,7 +155,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr *MI,
// was not a COPY, it would not be clear how to mirror that extension
// on the callee's side. For that reason, only check COPY instructions
// for potential extensions.
- if (MI->isCopy()) {
+ if (MI.isCopy()) {
if (evaluateFormalCopy(MI, Inputs, Outputs))
return true;
}
@@ -165,19 +166,19 @@ bool HexagonEvaluator::evaluate(const MachineInstr *MI,
// checking what kind of operand a given instruction has individually
// for each instruction, do it here. Global symbols as operands gene-
// rally do not provide any useful information.
- for (unsigned i = 0, n = MI->getNumOperands(); i < n; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
+ const MachineOperand &MO = MI.getOperand(i);
if (MO.isGlobal() || MO.isBlockAddress() || MO.isSymbol() || MO.isJTI() ||
MO.isCPI())
return false;
}
RegisterRefs Reg(MI);
- unsigned Opc = MI->getOpcode();
+ unsigned Opc = MI.getOpcode();
using namespace Hexagon;
- #define op(i) MI->getOperand(i)
- #define rc(i) RegisterCell::ref(getCell(Reg[i],Inputs))
- #define im(i) MI->getOperand(i).getImm()
+#define op(i) MI.getOperand(i)
+#define rc(i) RegisterCell::ref(getCell(Reg[i], Inputs))
+#define im(i) MI.getOperand(i).getImm()
// If the instruction has no register operands, skip it.
if (Reg.size() == 0)
@@ -190,9 +191,9 @@ bool HexagonEvaluator::evaluate(const MachineInstr *MI,
return true;
};
// Get the cell corresponding to the N-th operand.
- auto cop = [this,&Reg,&MI,&Inputs] (unsigned N, uint16_t W)
- -> BT::RegisterCell {
- const MachineOperand &Op = MI->getOperand(N);
+ auto cop = [this, &Reg, &MI, &Inputs](unsigned N,
+ uint16_t W) -> BT::RegisterCell {
+ const MachineOperand &Op = MI.getOperand(N);
if (Op.isImm())
return eIMM(Op.getImm(), W);
if (!Op.isReg())
@@ -879,13 +880,13 @@ bool HexagonEvaluator::evaluate(const MachineInstr *MI,
return false;
}
-
-bool HexagonEvaluator::evaluate(const MachineInstr *BI,
- const CellMapType &Inputs, BranchTargetList &Targets,
- bool &FallsThru) const {
+bool HexagonEvaluator::evaluate(const MachineInstr &BI,
+ const CellMapType &Inputs,
+ BranchTargetList &Targets,
+ bool &FallsThru) const {
// We need to evaluate one branch at a time. TII::AnalyzeBranch checks
// all the branches in a basic block at once, so we cannot use it.
- unsigned Opc = BI->getOpcode();
+ unsigned Opc = BI.getOpcode();
bool SimpleBranch = false;
bool Negated = false;
switch (Opc) {
@@ -901,7 +902,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr *BI,
SimpleBranch = true;
break;
case Hexagon::J2_jump:
- Targets.insert(BI->getOperand(0).getMBB());
+ Targets.insert(BI.getOperand(0).getMBB());
FallsThru = false;
return true;
default:
@@ -914,7 +915,7 @@ bool HexagonEvaluator::evaluate(const MachineInstr *BI,
return false;
// BI is a conditional branch if we got here.
- RegisterRef PR = BI->getOperand(0);
+ RegisterRef PR = BI.getOperand(0);
RegisterCell PC = getCell(PR, Inputs);
const BT::BitValue &Test = PC[0];
@@ -929,18 +930,18 @@ bool HexagonEvaluator::evaluate(const MachineInstr *BI,
return true;
}
- Targets.insert(BI->getOperand(1).getMBB());
+ Targets.insert(BI.getOperand(1).getMBB());
FallsThru = false;
return true;
}
-
-bool HexagonEvaluator::evaluateLoad(const MachineInstr *MI,
- const CellMapType &Inputs, CellMapType &Outputs) const {
- if (TII.isPredicated(*MI))
+bool HexagonEvaluator::evaluateLoad(const MachineInstr &MI,
+ const CellMapType &Inputs,
+ CellMapType &Outputs) const {
+ if (TII.isPredicated(MI))
return false;
- assert(MI->mayLoad() && "A load that mayn't?");
- unsigned Opc = MI->getOpcode();
+ assert(MI.mayLoad() && "A load that mayn't?");
+ unsigned Opc = MI.getOpcode();
uint16_t BitNum;
bool SignEx;
@@ -1067,7 +1068,7 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr *MI,
break;
}
- const MachineOperand &MD = MI->getOperand(0);
+ const MachineOperand &MD = MI.getOperand(0);
assert(MD.isReg() && MD.isDef());
RegisterRef RD = MD;
@@ -1091,15 +1092,15 @@ bool HexagonEvaluator::evaluateLoad(const MachineInstr *MI,
return true;
}
-
-bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr *MI,
- const CellMapType &Inputs, CellMapType &Outputs) const {
+bool HexagonEvaluator::evaluateFormalCopy(const MachineInstr &MI,
+ const CellMapType &Inputs,
+ CellMapType &Outputs) const {
// If MI defines a formal parameter, but is not a copy (loads are handled
// in evaluateLoad), then it's not clear what to do.
- assert(MI->isCopy());
+ assert(MI.isCopy());
- RegisterRef RD = MI->getOperand(0);
- RegisterRef RS = MI->getOperand(1);
+ RegisterRef RD = MI.getOperand(0);
+ RegisterRef RS = MI.getOperand(1);
assert(RD.Sub == 0);
if (!TargetRegisterInfo::isPhysicalRegister(RS.Reg))
return false;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.h b/llvm/lib/Target/Hexagon/HexagonBitTracker.h
index 897af2d7187..9e7b1dbe298 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.h
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.h
@@ -26,9 +26,9 @@ struct HexagonEvaluator : public BitTracker::MachineEvaluator {
HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
const HexagonInstrInfo &tii, MachineFunction &mf);
- bool evaluate(const MachineInstr *MI, const CellMapType &Inputs,
+ bool evaluate(const MachineInstr &MI, const CellMapType &Inputs,
CellMapType &Outputs) const override;
- bool evaluate(const MachineInstr *BI, const CellMapType &Inputs,
+ bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
BranchTargetList &Targets, bool &FallsThru) const override;
BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
@@ -38,9 +38,9 @@ struct HexagonEvaluator : public BitTracker::MachineEvaluator {
const HexagonInstrInfo &TII;
private:
- bool evaluateLoad(const MachineInstr *MI, const CellMapType &Inputs,
+ bool evaluateLoad(const MachineInstr &MI, const CellMapType &Inputs,
CellMapType &Outputs) const;
- bool evaluateFormalCopy(const MachineInstr *MI, const CellMapType &Inputs,
+ bool evaluateFormalCopy(const MachineInstr &MI, const CellMapType &Inputs,
CellMapType &Outputs) const;
unsigned getNextPhysReg(unsigned PReg, unsigned Width) const;
diff --git a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
index 58db4b75c72..559bdfb16a6 100644
--- a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
@@ -37,9 +37,9 @@ namespace {
class HexagonCFGOptimizer : public MachineFunctionPass {
private:
- void InvertAndChangeJumpTarget(MachineInstr*, MachineBasicBlock*);
+ void InvertAndChangeJumpTarget(MachineInstr &, MachineBasicBlock *);
- public:
+public:
static char ID;
HexagonCFGOptimizer() : MachineFunctionPass(ID) {
initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry());
@@ -68,14 +68,12 @@ static bool IsUnconditionalJump(int Opc) {
return (Opc == Hexagon::J2_jump);
}
-
-void
-HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI,
- MachineBasicBlock* NewTarget) {
+void HexagonCFGOptimizer::InvertAndChangeJumpTarget(
+ MachineInstr &MI, MachineBasicBlock *NewTarget) {
const TargetInstrInfo *TII =
- MI->getParent()->getParent()->getSubtarget().getInstrInfo();
+ MI.getParent()->getParent()->getSubtarget().getInstrInfo();
int NewOpcode = 0;
- switch(MI->getOpcode()) {
+ switch (MI.getOpcode()) {
case Hexagon::J2_jumpt:
NewOpcode = Hexagon::J2_jumpf;
break;
@@ -96,8 +94,8 @@ HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI,
llvm_unreachable("Cannot handle this case");
}
- MI->setDesc(TII->get(NewOpcode));
- MI->getOperand(1).setMBB(NewTarget);
+ MI.setDesc(TII->get(NewOpcode));
+ MI.getOperand(1).setMBB(NewTarget);
}
@@ -113,8 +111,8 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
// Traverse the basic block.
MachineBasicBlock::iterator MII = MBB->getFirstTerminator();
if (MII != MBB->end()) {
- MachineInstr *MI = MII;
- int Opc = MI->getOpcode();
+ MachineInstr &MI = *MII;
+ int Opc = MI.getOpcode();
if (IsConditionalBranch(Opc)) {
//
@@ -166,9 +164,9 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
// The target of the unconditional branch must be JumpAroundTarget.
// TODO: If not, we should not invert the unconditional branch.
MachineBasicBlock* CondBranchTarget = nullptr;
- if ((MI->getOpcode() == Hexagon::J2_jumpt) ||
- (MI->getOpcode() == Hexagon::J2_jumpf)) {
- CondBranchTarget = MI->getOperand(1).getMBB();
+ if (MI.getOpcode() == Hexagon::J2_jumpt ||
+ MI.getOpcode() == Hexagon::J2_jumpf) {
+ CondBranchTarget = MI.getOperand(1).getMBB();
}
if (!LayoutSucc || (CondBranchTarget != JumpAroundTarget)) {
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 8911ab3782c..face0f3f64b 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -92,16 +92,16 @@ public:
}
private:
- MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1,
+ MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1,
bool AllowC64);
void findPotentialNewifiableTFRs(MachineBasicBlock &);
- void combine(MachineInstr *I1, MachineInstr *I2,
+ void combine(MachineInstr &I1, MachineInstr &I2,
MachineBasicBlock::iterator &MI, bool DoInsertAtI1,
bool OptForSize);
- bool isSafeToMoveTogether(MachineInstr *I1, MachineInstr *I2,
+ bool isSafeToMoveTogether(MachineInstr &I1, MachineInstr &I2,
unsigned I1DestReg, unsigned I2DestReg,
bool &DoInsertAtI1);
@@ -128,14 +128,13 @@ char HexagonCopyToCombine::ID = 0;
INITIALIZE_PASS(HexagonCopyToCombine, "hexagon-copy-combine",
"Hexagon Copy-To-Combine Pass", false, false)
-static bool isCombinableInstType(MachineInstr *MI,
- const HexagonInstrInfo *TII,
+static bool isCombinableInstType(MachineInstr &MI, const HexagonInstrInfo *TII,
bool ShouldCombineAggressively) {
- switch(MI->getOpcode()) {
+ switch (MI.getOpcode()) {
case Hexagon::A2_tfr: {
// A COPY instruction can be combined if its arguments are IntRegs (32bit).
- const MachineOperand &Op0 = MI->getOperand(0);
- const MachineOperand &Op1 = MI->getOperand(1);
+ const MachineOperand &Op0 = MI.getOperand(0);
+ const MachineOperand &Op1 = MI.getOperand(1);
assert(Op0.isReg() && Op1.isReg());
unsigned DestReg = Op0.getReg();
@@ -147,8 +146,8 @@ static bool isCombinableInstType(MachineInstr *MI,
case Hexagon::A2_tfrsi: {
// A transfer-immediate can be combined if its argument is a signed 8bit
// value.
- const MachineOperand &Op0 = MI->getOperand(0);
- const MachineOperand &Op1 = MI->getOperand(1);
+ const MachineOperand &Op0 = MI.getOperand(0);
+ const MachineOperand &Op1 = MI.getOperand(1);
assert(Op0.isReg());
unsigned DestReg = Op0.getReg();
@@ -171,11 +170,10 @@ static bool isCombinableInstType(MachineInstr *MI,
return false;
}
-template <unsigned N>
-static bool isGreaterThanNBitTFRI(const MachineInstr *I) {
- if (I->getOpcode() == Hexagon::TFRI64_V4 ||
- I->getOpcode() == Hexagon::A2_tfrsi) {
- const MachineOperand &Op = I->getOperand(1);
+template <unsigned N> static bool isGreaterThanNBitTFRI(const MachineInstr &I) {
+ if (I.getOpcode() == Hexagon::TFRI64_V4 ||
+ I.getOpcode() == Hexagon::A2_tfrsi) {
+ const MachineOperand &Op = I.getOperand(1);
return !Op.isImm() || !isInt<N>(Op.getImm());
}
return false;
@@ -184,10 +182,10 @@ static bool isGreaterThanNBitTFRI(const MachineInstr *I) {
/// areCombinableOperations - Returns true if the two instruction can be merge
/// into a combine (ignoring register constraints).
static bool areCombinableOperations(const TargetRegisterInfo *TRI,
- MachineInstr *HighRegInst,
- MachineInstr *LowRegInst, bool AllowC64) {
- unsigned HiOpc = HighRegInst->getOpcode();
- unsigned LoOpc = LowRegInst->getOpcode();
+ MachineInstr &HighRegInst,
+ MachineInstr &LowRegInst, bool AllowC64) {
+ unsigned HiOpc = HighRegInst.getOpcode();
+ unsigned LoOpc = LowRegInst.getOpcode();
(void)HiOpc; // Fix compiler warning
(void)LoOpc; // Fix compiler warning
assert((HiOpc == Hexagon::A2_tfr || HiOpc == Hexagon::A2_tfrsi) &&
@@ -205,8 +203,8 @@ static bool areCombinableOperations(const TargetRegisterInfo *TRI,
// provided both constants are true immediates.
if (isGreaterThanNBitTFRI<16>(HighRegInst) &&
isGreaterThanNBitTFRI<16>(LowRegInst))
- return (HighRegInst->getOperand(1).isImm() &&
- LowRegInst->getOperand(1).isImm());
+ return (HighRegInst.getOperand(1).isImm() &&
+ LowRegInst.getOperand(1).isImm());
// There is no combine of two constant extended values, unless handled above
// Make both 8-bit size checks to allow both combine (#,##) and combine(##,#)
@@ -223,25 +221,23 @@ static bool isEvenReg(unsigned Reg) {
return (Reg - Hexagon::R0) % 2 == 0;
}
-static void removeKillInfo(MachineInstr *MI, unsigned RegNotKilled) {
- for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
- MachineOperand &Op = MI->getOperand(I);
+static void removeKillInfo(MachineInstr &MI, unsigned RegNotKilled) {
+ for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
+ MachineOperand &Op = MI.getOperand(I);
if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
continue;
Op.setIsKill(false);
}
}
-/// isUnsafeToMoveAcross - Returns true if it is unsafe to move a copy
-/// instruction from \p UseReg to \p DestReg over the instruction \p I.
-static bool isUnsafeToMoveAcross(MachineInstr *I, unsigned UseReg,
- unsigned DestReg,
- const TargetRegisterInfo *TRI) {
- return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
- I->modifiesRegister(DestReg, TRI) ||
- I->readsRegister(DestReg, TRI) ||
- I->hasUnmodeledSideEffects() ||
- I->isInlineAsm() || I->isDebugValue();
+/// Returns true if it is unsafe to move a copy instruction from \p UseReg to
+/// \p DestReg over the instruction \p MI.
+static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg,
+ unsigned DestReg,
+ const TargetRegisterInfo *TRI) {
+ return (UseReg && (MI.modifiesRegister(UseReg, TRI))) ||
+ MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) ||
+ MI.hasUnmodeledSideEffects() || MI.isInlineAsm() || MI.isDebugValue();
}
static unsigned UseReg(const MachineOperand& MO) {
@@ -250,16 +246,16 @@ static unsigned UseReg(const MachineOperand& MO) {
/// isSafeToMoveTogether - Returns true if it is safe to move I1 next to I2 such
/// that the two instructions can be paired in a combine.
-bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
- MachineInstr *I2,
+bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1,
+ MachineInstr &I2,
unsigned I1DestReg,
unsigned I2DestReg,
bool &DoInsertAtI1) {
- unsigned I2UseReg = UseReg(I2->getOperand(1));
+ unsigned I2UseReg = UseReg(I2.getOperand(1));
// It is not safe to move I1 and I2 into one combine if I2 has a true
// dependence on I1.
- if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
+ if (I2UseReg && I1.modifiesRegister(I2UseReg, TRI))
return false;
bool isSafe = true;
@@ -278,7 +274,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
// uses I2's use reg we need to modify that (first) instruction to now kill
// this reg.
unsigned KilledOperand = 0;
- if (I2->killsRegister(I2UseReg))
+ if (I2.killsRegister(I2UseReg))
KilledOperand = I2UseReg;
MachineInstr *KillingInstr = nullptr;
@@ -292,7 +288,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
if (I->isDebugValue())
continue;
- if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
+ if (isUnsafeToMoveAcross(*I, I2UseReg, I2DestReg, TRI)) {
isSafe = false;
break;
}
@@ -322,7 +318,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
// At O3 we got better results (dhrystone) by being more conservative here.
if (!ShouldCombineAggressively)
End = std::next(MachineBasicBlock::iterator(I2));
- unsigned I1UseReg = UseReg(I1->getOperand(1));
+ unsigned I1UseReg = UseReg(I1.getOperand(1));
// Track killed operands. If we move across an instruction that kills our
// operand, we need to update the kill information on the moved I1. It kills
// the operand now.
@@ -330,7 +326,8 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
unsigned KilledOperand = 0;
while(++I != End) {
- // If the intervening instruction I:
+ MachineInstr &MI = *I;
+ // If the intervening instruction MI:
// * modifies I1's use reg
// * modifies I1's def reg
// * reads I1's def reg
@@ -346,29 +343,29 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
// to remove the %D4<imp-use,kill> operand. For now, we are
// conservative and disallow the move.
// we can't move I1 across it.
- if (I->isDebugValue()) {
- if (I->readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
- DbgMItoMove.push_back(I);
+ if (MI.isDebugValue()) {
+ if (MI.readsRegister(I1DestReg, TRI)) // Move this instruction after I2.
+ DbgMItoMove.push_back(&MI);
continue;
}
- if (isUnsafeToMoveAcross(I, I1UseReg, I1DestReg, TRI) ||
+ if (isUnsafeToMoveAcross(MI, I1UseReg, I1DestReg, TRI) ||
// Check for an aliased register kill. Bail out if we see one.
- (!I->killsRegister(I1UseReg) && I->killsRegister(I1UseReg, TRI)))
+ (!MI.killsRegister(I1UseReg) && MI.killsRegister(I1UseReg, TRI)))
return false;
// Check for an exact kill (registers match).
- if (I1UseReg && I->killsRegister(I1UseReg)) {
+ if (I1UseReg && MI.killsRegister(I1UseReg)) {
assert(!KillingInstr && "Should only see one killing instruction");
KilledOperand = I1UseReg;
- KillingInstr = &*I;
+ KillingInstr = &MI;
}
}
if (KillingInstr) {
- removeKillInfo(KillingInstr, KilledOperand);
+ removeKillInfo(*KillingInstr, KilledOperand);
// Update I1 to set the kill flag. This flag will later be picked up by
// the new COMBINE instruction.
- bool Added = I1->addRegisterKilled(KilledOperand, TRI);
+ bool Added = I1.addRegisterKilled(KilledOperand, TRI);
(void)Added; // suppress compiler warning
assert(Added && "Must successfully update kill flag");
}
@@ -383,17 +380,16 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr *I1,
void
HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
DenseMap<unsigned, MachineInstr *> LastDef;
- for (MachineBasicBlock::iterator I = BB.begin(), E = BB.end(); I != E; ++I) {
- MachineInstr *MI = I;
- if (MI->isDebugValue())
+ for (MachineInstr &MI : BB) {
+ if (MI.isDebugValue())
continue;
// Mark TFRs that feed a potential new value store as such.
- if(TII->mayBeNewStore(MI)) {
+ if (TII->mayBeNewStore(&MI)) {
// Look for uses of TFR instructions.
- for (unsigned OpdIdx = 0, OpdE = MI->getNumOperands(); OpdIdx != OpdE;
+ for (unsigned OpdIdx = 0, OpdE = MI.getNumOperands(); OpdIdx != OpdE;
++OpdIdx) {
- MachineOperand &Op = MI->getOperand(OpdIdx);
+ MachineOperand &Op = MI.getOperand(OpdIdx);
// Skip over anything except register uses.
if (!Op.isReg() || !Op.isUse() || !Op.getReg())
@@ -404,14 +400,14 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
MachineInstr *DefInst = LastDef[Reg];
if (!DefInst)
continue;
- if (!isCombinableInstType(DefInst, TII, ShouldCombineAggressively))
+ if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively))
continue;
// Only close newifiable stores should influence the decision.
// Ignore the debug instructions in between.
MachineBasicBlock::iterator It(DefInst);
unsigned NumInstsToDef = 0;
- while (&*It != MI) {
+ while (&*It != &MI) {
if (!It->isDebugValue())
++NumInstsToDef;
++It;
@@ -428,17 +424,17 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
// Put instructions that last defined integer or double registers into the
// map.
- for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
- MachineOperand &Op = MI->getOperand(I);
+ for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
+ MachineOperand &Op = MI.getOperand(I);
if (!Op.isReg() || !Op.isDef() || !Op.getReg())
continue;
unsigned Reg = Op.getReg();
if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
- LastDef[*SubRegs] = MI;
+ LastDef[*SubRegs] = &MI;
}
} else if (Hexagon::IntRegsRegClass.contains(Reg))
- LastDef[Reg] = MI;
+ LastDef[Reg] = &MI;
}
}
}
@@ -469,15 +465,15 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
// Traverse instructions in basic block.
for(MachineBasicBlock::iterator MI = BI->begin(), End = BI->end();
MI != End;) {
- MachineInstr *I1 = MI++;
+ MachineInstr &I1 = *MI++;
- if (I1->isDebugValue())
+ if (I1.isDebugValue())
continue;
// Don't combine a TFR whose user could be newified (instructions that
// define double registers can not be newified - Programmer's Ref Manual
// 5.4.2 New-value stores).
- if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I1))
+ if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&I1))
continue;
// Ignore instructions that are not combinable.
@@ -492,7 +488,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
MachineInstr *I2 = findPairable(I1, DoInsertAtI1, OptForSize);
if (I2) {
HasChanged = true;
- combine(I1, I2, MI, DoInsertAtI1, OptForSize);
+ combine(I1, *I2, MI, DoInsertAtI1, OptForSize);
}
}
}
@@ -504,7 +500,7 @@ bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) {
/// COMBINE instruction or 0 if no such instruction can be found. Returns true
/// in \p DoInsertAtI1 if the combine must be inserted at instruction \p I1
/// false if the combine must be inserted at the returned instruction.
-MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
+MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr &I1,
bool &DoInsertAtI1,
bool AllowC64) {
MachineBasicBlock::iterator I2 = std::next(MachineBasicBlock::iterator(I1));
@@ -512,20 +508,20 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
while (I2->isDebugValue())
++I2;
- unsigned I1DestReg = I1->getOperand(0).getReg();
+ unsigned I1DestReg = I1.getOperand(0).getReg();
- for (MachineBasicBlock::iterator End = I1->getParent()->end(); I2 != End;
+ for (MachineBasicBlock::iterator End = I1.getParent()->end(); I2 != End;
++I2) {
// Bail out early if we see a second definition of I1DestReg.
if (I2->modifiesRegister(I1DestReg, TRI))
break;
// Ignore non-combinable instructions.
- if (!isCombinableInstType(I2, TII, ShouldCombineAggressively))
+ if (!isCombinableInstType(*I2, TII, ShouldCombineAggressively))
continue;
// Don't combine a TFR whose user could be newified.
- if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(I2))
+ if (ShouldCombineAggressively && PotentiallyNewifiableTFR.count(&*I2))
continue;
unsigned I2DestReg = I2->getOperand(0).getReg();
@@ -542,13 +538,12 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
// instructions to be merged into a combine.
// The order matters because in a A2_tfrsi we might can encode a int8 as
// the hi reg operand but only a uint6 as the low reg operand.
- if ((IsI2LowReg && !areCombinableOperations(TRI, I1, I2, AllowC64)) ||
- (IsI1LowReg && !areCombinableOperations(TRI, I2, I1, AllowC64)))
+ if ((IsI2LowReg && !areCombinableOperations(TRI, I1, *I2, AllowC64)) ||
+ (IsI1LowReg && !areCombinableOperations(TRI, *I2, I1, AllowC64)))
break;
- if (isSafeToMoveTogether(I1, I2, I1DestReg, I2DestReg,
- DoInsertAtI1))
- return I2;
+ if (isSafeToMoveTogether(I1, *I2, I1DestReg, I2DestReg, DoInsertAtI1))
+ return &*I2;
// Not safe. Stop searching.
break;
@@ -556,16 +551,17 @@ MachineInstr *HexagonCopyToCombine::findPairable(MachineInstr *I1,
return nullptr;
}
-void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
+void HexagonCopyToCombine::combine(MachineInstr &I1, MachineInstr &I2,
MachineBasicBlock::iterator &MI,
bool DoInsertAtI1, bool OptForSize) {
// We are going to delete I2. If MI points to I2 advance it to the next
// instruction.
- if ((MachineInstr *)MI == I2) ++MI;
+ if (MI == I2.getIterator())
+ ++MI;
// Figure out whether I1 or I2 goes into the lowreg part.
- unsigned I1DestReg = I1->getOperand(0).getReg();
- unsigned I2DestReg = I2->getOperand(0).getReg();
+ unsigned I1DestReg = I1.getOperand(0).getReg();
+ unsigned I2DestReg = I2.getOperand(0).getReg();
bool IsI1Loreg = (I2DestReg - I1DestReg) == 1;
unsigned LoRegDef = IsI1Loreg ? I1DestReg : I2DestReg;
@@ -577,10 +573,8 @@ void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
// Setup source operands.
- MachineOperand &LoOperand = IsI1Loreg ? I1->getOperand(1) :
- I2->getOperand(1);
- MachineOperand &HiOperand = IsI1Loreg ? I2->getOperand(1) :
- I1->getOperand(1);
+ MachineOperand &LoOperand = IsI1Loreg ? I1.getOperand(1) : I2.getOperand(1);
+ MachineOperand &HiOperand = IsI1Loreg ? I2.getOperand(1) : I1.getOperand(1);
// Figure out which source is a register and which a constant.
bool IsHiReg = HiOperand.isReg();
@@ -617,8 +611,8 @@ void HexagonCopyToCombine::combine(MachineInstr *I1, MachineInstr *I2,
}
}
- I1->eraseFromParent();
- I2->eraseFromParent();
+ I1.eraseFromParent();
+ I2.eraseFromParent();
}
void HexagonCopyToCombine::emitConst64(MachineBasicBlock::iterator &InsertPt,
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 6f65e2203a6..bd5bb9cbc23 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -230,7 +230,7 @@ namespace {
enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) };
enum { Exec_Then = 0x10, Exec_Else = 0x20 };
unsigned getMaskForSub(unsigned Sub);
- bool isCondset(const MachineInstr *MI);
+ bool isCondset(const MachineInstr &MI);
LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
@@ -241,7 +241,7 @@ namespace {
void updateKillFlags(unsigned Reg);
void updateDeadFlags(unsigned Reg);
void recalculateLiveInterval(unsigned Reg);
- void removeInstr(MachineInstr *MI);
+ void removeInstr(MachineInstr &MI);
void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
bool UpdateKills, bool UpdateDeads);
@@ -250,22 +250,22 @@ namespace {
MachineBasicBlock::iterator At, unsigned DstR,
unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
bool ReadUndef, bool ImpUse);
- bool split(MachineInstr *MI, std::set<unsigned> &UpdRegs);
+ bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
bool splitInBlock(MachineBasicBlock &B, std::set<unsigned> &UpdRegs);
bool isPredicable(MachineInstr *MI);
MachineInstr *getReachingDefForPred(RegisterRef RD,
MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
- bool canMoveOver(MachineInstr *MI, ReferenceMap &Defs, ReferenceMap &Uses);
- bool canMoveMemTo(MachineInstr *MI, MachineInstr *ToI, bool IsDown);
- void predicateAt(const MachineOperand &DefOp, MachineInstr *MI,
- MachineBasicBlock::iterator Where, const MachineOperand &PredOp,
- bool Cond, std::set<unsigned> &UpdRegs);
+ bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
+ bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown);
+ void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
+ MachineBasicBlock::iterator Where,
+ const MachineOperand &PredOp, bool Cond,
+ std::set<unsigned> &UpdRegs);
void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
bool Cond, MachineBasicBlock::iterator First,
MachineBasicBlock::iterator Last);
- bool predicate(MachineInstr *TfrI, bool Cond,
- std::set<unsigned> &UpdRegs);
+ bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
bool predicateInBlock(MachineBasicBlock &B,
std::set<unsigned> &UpdRegs);
@@ -298,9 +298,8 @@ unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
llvm_unreachable("Invalid subregister");
}
-
-bool HexagonExpandCondsets::isCondset(const MachineInstr *MI) {
- unsigned Opc = MI->getOpcode();
+bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
+ unsigned Opc = MI.getOpcode();
switch (Opc) {
case Hexagon::C2_mux:
case Hexagon::C2_muxii:
@@ -548,10 +547,9 @@ void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
LIS->createAndComputeVirtRegInterval(Reg);
}
-
-void HexagonExpandCondsets::removeInstr(MachineInstr *MI) {
- LIS->RemoveMachineInstrFromMaps(*MI);
- MI->eraseFromParent();
+void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
+ LIS->RemoveMachineInstrFromMaps(MI);
+ MI.eraseFromParent();
}
@@ -640,19 +638,19 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
/// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
/// performs all necessary changes to complete the replacement.
-bool HexagonExpandCondsets::split(MachineInstr *MI,
- std::set<unsigned> &UpdRegs) {
+bool HexagonExpandCondsets::split(MachineInstr &MI,
+ std::set<unsigned> &UpdRegs) {
if (TfrLimitActive) {
if (TfrCounter >= TfrLimit)
return false;
TfrCounter++;
}
- DEBUG(dbgs() << "\nsplitting BB#" << MI->getParent()->getNumber()
- << ": " << *MI);
- MachineOperand &MD = MI->getOperand(0); // Definition
- MachineOperand &MP = MI->getOperand(1); // Predicate register
- MachineOperand &MS1 = MI->getOperand(2); // Source value #1
- MachineOperand &MS2 = MI->getOperand(3); // Source value #2
+ DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": "
+ << MI);
+ MachineOperand &MD = MI.getOperand(0); // Definition
+ MachineOperand &MP = MI.getOperand(1); // Predicate register
+ MachineOperand &MS1 = MI.getOperand(2); // Source value #1
+ MachineOperand &MS2 = MI.getOperand(3); // Source value #2
assert(MD.isDef());
unsigned DR = MD.getReg(), DSR = MD.getSubReg();
bool ReadUndef = MD.isUndef();
@@ -685,15 +683,15 @@ bool HexagonExpandCondsets::split(MachineInstr *MI,
// First, create the two invididual conditional transfers, and add each
// of them to the live intervals information. Do that first and then remove
// the old instruction from live intervals.
- MachineInstr *TfrT = genCondTfrFor(MI->getOperand(2), At, DR, DSR, MP, true,
- ReadUndef, false);
- MachineInstr *TfrF = genCondTfrFor(MI->getOperand(3), At, DR, DSR, MP, false,
- ReadUndef, true);
+ MachineInstr *TfrT =
+ genCondTfrFor(MI.getOperand(2), At, DR, DSR, MP, true, ReadUndef, false);
+ MachineInstr *TfrF =
+ genCondTfrFor(MI.getOperand(3), At, DR, DSR, MP, false, ReadUndef, true);
LIS->InsertMachineInstrInMaps(*TfrT);
LIS->InsertMachineInstrInMaps(*TfrF);
// Will need to recalculate live intervals for all registers in MI.
- for (auto &Op : MI->operands())
+ for (auto &Op : MI.operands())
if (Op.isReg())
UpdRegs.insert(Op.getReg());
@@ -710,8 +708,8 @@ bool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B,
MachineBasicBlock::iterator I, E, NextI;
for (I = B.begin(), E = B.end(); I != E; I = NextI) {
NextI = std::next(I);
- if (isCondset(I))
- Changed |= split(I, UpdRegs);
+ if (isCondset(*I))
+ Changed |= split(*I, UpdRegs);
}
return Changed;
}
@@ -791,12 +789,12 @@ MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
/// the maps Defs and Uses. These maps reflect the conditional defs and uses
/// that depend on the same predicate register to allow moving instructions
/// over instructions predicated on the opposite condition.
-bool HexagonExpandCondsets::canMoveOver(MachineInstr *MI, ReferenceMap &Defs,
- ReferenceMap &Uses) {
+bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
+ ReferenceMap &Uses) {
// In order to be able to safely move MI over instructions that define
// "Defs" and use "Uses", no def operand from MI can be defined or used
// and no use operand can be defined.
- for (auto &Op : MI->operands()) {
+ for (auto &Op : MI.operands()) {
if (!Op.isReg())
continue;
RegisterRef RR = Op;
@@ -818,19 +816,19 @@ bool HexagonExpandCondsets::canMoveOver(MachineInstr *MI, ReferenceMap &Defs,
/// Check if the instruction accessing memory (TheI) can be moved to the
/// location ToI.
-bool HexagonExpandCondsets::canMoveMemTo(MachineInstr *TheI, MachineInstr *ToI,
- bool IsDown) {
- bool IsLoad = TheI->mayLoad(), IsStore = TheI->mayStore();
+bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI,
+ bool IsDown) {
+ bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
if (!IsLoad && !IsStore)
return true;
- if (HII->areMemAccessesTriviallyDisjoint(*TheI, *ToI))
+ if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
return true;
- if (TheI->hasUnmodeledSideEffects())
+ if (TheI.hasUnmodeledSideEffects())
return false;
MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI;
MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI;
- bool Ordered = TheI->hasOrderedMemoryRef();
+ bool Ordered = TheI.hasOrderedMemoryRef();
// Search for aliased memory reference in (StartI, EndI).
for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
@@ -854,8 +852,10 @@ bool HexagonExpandCondsets::canMoveMemTo(MachineInstr *TheI, MachineInstr *ToI,
/// Generate a predicated version of MI (where the condition is given via
/// PredR and Cond) at the point indicated by Where.
void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
- MachineInstr *MI, MachineBasicBlock::iterator Where,
- const MachineOperand &PredOp, bool Cond, std::set<unsigned> &UpdRegs) {
+ MachineInstr &MI,
+ MachineBasicBlock::iterator Where,
+ const MachineOperand &PredOp, bool Cond,
+ std::set<unsigned> &UpdRegs) {
// The problem with updating live intervals is that we can move one def
// past another def. In particular, this can happen when moving an A2_tfrt
// over an A2_tfrf defining the same register. From the point of view of
@@ -867,15 +867,15 @@ void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
// target location, (2) update liveness, (3) delete the old instruction,
// and (4) update liveness again.
- MachineBasicBlock &B = *MI->getParent();
+ MachineBasicBlock &B = *MI.getParent();
DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
- unsigned Opc = MI->getOpcode();
+ unsigned Opc = MI.getOpcode();
unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
- unsigned Ox = 0, NP = MI->getNumOperands();
+ unsigned Ox = 0, NP = MI.getNumOperands();
// Skip all defs from MI first.
while (Ox < NP) {
- MachineOperand &MO = MI->getOperand(Ox);
+ MachineOperand &MO = MI.getOperand(Ox);
if (!MO.isReg() || !MO.isDef())
break;
Ox++;
@@ -886,15 +886,15 @@ void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
PredOp.getSubReg());
while (Ox < NP) {
- MachineOperand &MO = MI->getOperand(Ox);
+ MachineOperand &MO = MI.getOperand(Ox);
if (!MO.isReg() || !MO.isImplicit())
MB.addOperand(MO);
Ox++;
}
MachineFunction &MF = *B.getParent();
- MachineInstr::mmo_iterator I = MI->memoperands_begin();
- unsigned NR = std::distance(I, MI->memoperands_end());
+ MachineInstr::mmo_iterator I = MI.memoperands_begin();
+ unsigned NR = std::distance(I, MI.memoperands_end());
MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR);
for (unsigned i = 0; i < NR; ++i)
MemRefs[i] = *I++;
@@ -941,18 +941,18 @@ void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
/// For a given conditional copy, predicate the definition of the source of
/// the copy under the given condition (using the same predicate register as
/// the copy).
-bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond,
- std::set<unsigned> &UpdRegs) {
+bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
+ std::set<unsigned> &UpdRegs) {
// TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
- unsigned Opc = TfrI->getOpcode();
+ unsigned Opc = TfrI.getOpcode();
(void)Opc;
assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf);
DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
- << ": " << *TfrI);
+ << ": " << TfrI);
- MachineOperand &MD = TfrI->getOperand(0);
- MachineOperand &MP = TfrI->getOperand(1);
- MachineOperand &MS = TfrI->getOperand(2);
+ MachineOperand &MD = TfrI.getOperand(0);
+ MachineOperand &MP = TfrI.getOperand(1);
+ MachineOperand &MS = TfrI.getOperand(2);
// The source operand should be a <kill>. This is not strictly necessary,
// but it makes things a lot simpler. Otherwise, we would need to rename
// some registers, which would complicate the transformation considerably.
@@ -1040,20 +1040,20 @@ bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond,
// If the target register of the TfrI (RD) is not used or defined between
// DefI and TfrI, consider moving TfrI up to DefI.
bool CanUp = canMoveOver(TfrI, Defs, Uses);
- bool CanDown = canMoveOver(DefI, Defs, Uses);
+ bool CanDown = canMoveOver(*DefI, Defs, Uses);
// The TfrI does not access memory, but DefI could. Check if it's safe
// to move DefI down to TfrI.
if (DefI->mayLoad() || DefI->mayStore())
- if (!canMoveMemTo(DefI, TfrI, true))
+ if (!canMoveMemTo(*DefI, TfrI, true))
CanDown = false;
DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
<< ", can move down: " << (CanDown ? "yes\n" : "no\n"));
MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
if (CanUp)
- predicateAt(MD, DefI, PastDefIt, MP, Cond, UpdRegs);
+ predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs);
else if (CanDown)
- predicateAt(MD, DefI, TfrIt, MP, Cond, UpdRegs);
+ predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs);
else
return false;
@@ -1063,7 +1063,7 @@ bool HexagonExpandCondsets::predicate(MachineInstr *TfrI, bool Cond,
}
removeInstr(TfrI);
- removeInstr(DefI);
+ removeInstr(*DefI);
return true;
}
@@ -1077,7 +1077,7 @@ bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
NextI = std::next(I);
unsigned Opc = I->getOpcode();
if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) {
- bool Done = predicate(I, (Opc == Hexagon::A2_tfrt), UpdRegs);
+ bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
if (!Done) {
// If we didn't predicate I, we may need to remove it in case it is
// an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1.
@@ -1085,7 +1085,7 @@ bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
for (auto &Op : I->operands())
if (Op.isReg())
UpdRegs.insert(Op.getReg());
- removeInstr(&*I);
+ removeInstr(*I);
}
}
Changed |= Done;
@@ -1194,7 +1194,7 @@ bool HexagonExpandCondsets::coalesceSegments(MachineFunction &MF) {
MachineBasicBlock &B = *I;
for (MachineBasicBlock::iterator J = B.begin(), F = B.end(); J != F; ++J) {
MachineInstr *MI = &*J;
- if (!isCondset(MI))
+ if (!isCondset(*MI))
continue;
MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
if (!S1.isReg() && !S2.isReg())
@@ -1292,7 +1292,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
updateLiveness(Diff, false, false, true);
for (auto *ImpD : LocalImpDefs)
- removeInstr(ImpD);
+ removeInstr(*ImpD);
DEBUG({
if (Changed)
diff --git a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
index e86019ee493..3de817cc8fb 100644
--- a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
@@ -82,11 +82,11 @@ FunctionPass *llvm::createHexagonFixupHwLoops() {
}
/// \brief Returns true if the instruction is a hardware loop instruction.
-static bool isHardwareLoop(const MachineInstr *MI) {
- return MI->getOpcode() == Hexagon::J2_loop0r ||
- MI->getOpcode() == Hexagon::J2_loop0i ||
- MI->getOpcode() == Hexagon::J2_loop1r ||
- MI->getOpcode() == Hexagon::J2_loop1i;
+static bool isHardwareLoop(const MachineInstr &MI) {
+ return MI.getOpcode() == Hexagon::J2_loop0r ||
+ MI.getOpcode() == Hexagon::J2_loop0i ||
+ MI.getOpcode() == Hexagon::J2_loop1r ||
+ MI.getOpcode() == Hexagon::J2_loop1i;
}
bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) {
@@ -143,7 +143,7 @@ bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) {
++MII;
continue;
}
- if (isHardwareLoop(MII)) {
+ if (isHardwareLoop(*MII)) {
assert(MII->getOperand(0).isMBB() &&
"Expect a basic block as loop operand");
int diff = InstOffset - BlockToInstOffset[MII->getOperand(0).getMBB()];
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
index fb6bbf79b9b..bb9256db4b4 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -74,10 +74,10 @@ namespace {
MachineOperand *SrcT, *SrcF;
MachineInstr *Def1, *Def2;
MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR,
- MachineOperand *TOp, MachineOperand *FOp,
- MachineInstr *D1, MachineInstr *D2)
- : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1),
- Def2(D2) {}
+ MachineOperand *TOp, MachineOperand *FOp, MachineInstr &D1,
+ MachineInstr &D2)
+ : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1),
+ Def2(&D2) {}
};
typedef DenseMap<MachineInstr*,unsigned> InstrIndexMap;
typedef DenseMap<unsigned,DefUseInfo> DefUseInfoMap;
@@ -262,8 +262,8 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) {
MachineBasicBlock::iterator It1 = B.begin(), It2 = B.begin();
std::advance(It1, MinX);
std::advance(It2, MaxX);
- MachineInstr *Def1 = It1, *Def2 = It2;
- MachineOperand *Src1 = &Def1->getOperand(2), *Src2 = &Def2->getOperand(2);
+ MachineInstr &Def1 = *It1, &Def2 = *It2;
+ MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0;
unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0;
bool Failure = false, CanUp = true, CanDown = true;
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 204f11ce151..dcfd3e8317a 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -447,13 +447,12 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
// the convertible instruction is converted, its predicate result will be
// copied back into the original gpr.
- for (MachineFunction::iterator A = MF.begin(), Z = MF.end(); A != Z; ++A) {
- MachineBasicBlock &B = *A;
- for (MachineBasicBlock::iterator I = B.begin(), E = B.end(); I != E; ++I) {
- if (I->getOpcode() != TargetOpcode::COPY)
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ if (MI.getOpcode() != TargetOpcode::COPY)
continue;
- Register DR = I->getOperand(0);
- Register SR = I->getOperand(1);
+ Register DR = MI.getOperand(0);
+ Register SR = MI.getOperand(1);
if (!TargetRegisterInfo::isVirtualRegister(DR.R))
continue;
if (!TargetRegisterInfo::isVirtualRegister(SR.R))
@@ -464,7 +463,7 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
continue;
assert(!DR.S && !SR.S && "Unexpected subregister");
MRI->replaceRegWith(DR.R, SR.R);
- Erase.insert(I);
+ Erase.insert(&MI);
Changed = true;
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
index fbc8113c118..3ffb9cffc6a 100644
--- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -93,7 +93,7 @@ namespace {
/// \brief A handle to the branch probability pass.
const MachineBranchProbabilityInfo *MBPI;
- bool isNewValueJumpCandidate(const MachineInstr *MI) const;
+ bool isNewValueJumpCandidate(const MachineInstr &MI) const;
};
} // end of anonymous namespace
@@ -220,25 +220,24 @@ static bool canCompareBeNewValueJump(const HexagonInstrInfo *QII,
MachineBasicBlock::iterator end,
MachineFunction &MF) {
- MachineInstr *MI = II;
+ MachineInstr &MI = *II;
// If the second operand of the compare is an imm, make sure it's in the
// range specified by the arch.
if (!secondReg) {
- int64_t v = MI->getOperand(2).getImm();
+ int64_t v = MI.getOperand(2).getImm();
- if (!(isUInt<5>(v) ||
- ((MI->getOpcode() == Hexagon::C2_cmpeqi ||
- MI->getOpcode() == Hexagon::C2_cmpgti) &&
- (v == -1))))
+ if (!(isUInt<5>(v) || ((MI.getOpcode() == Hexagon::C2_cmpeqi ||
+ MI.getOpcode() == Hexagon::C2_cmpgti) &&
+ (v == -1))))
return false;
}
unsigned cmpReg1, cmpOp2 = 0; // cmpOp2 assignment silences compiler warning.
- cmpReg1 = MI->getOperand(1).getReg();
+ cmpReg1 = MI.getOperand(1).getReg();
if (secondReg) {
- cmpOp2 = MI->getOperand(2).getReg();
+ cmpOp2 = MI.getOperand(2).getReg();
// Make sure that that second register is not from COPY
// At machine code level, we don't need this, but if we decide
@@ -368,22 +367,22 @@ static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
return 0;
}
-bool HexagonNewValueJump::isNewValueJumpCandidate(const MachineInstr *MI)
- const {
- switch (MI->getOpcode()) {
- case Hexagon::C2_cmpeq:
- case Hexagon::C2_cmpeqi:
- case Hexagon::C2_cmpgt:
- case Hexagon::C2_cmpgti:
- case Hexagon::C2_cmpgtu:
- case Hexagon::C2_cmpgtui:
- case Hexagon::C4_cmpneq:
- case Hexagon::C4_cmplte:
- case Hexagon::C4_cmplteu:
- return true;
-
- default:
- return false;
+bool HexagonNewValueJump::isNewValueJumpCandidate(
+ const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
+ case Hexagon::C2_cmpeq:
+ case Hexagon::C2_cmpeqi:
+ case Hexagon::C2_cmpgt:
+ case Hexagon::C2_cmpgti:
+ case Hexagon::C2_cmpgtu:
+ case Hexagon::C2_cmpgtui:
+ case Hexagon::C4_cmpneq:
+ case Hexagon::C4_cmplte:
+ case Hexagon::C4_cmplteu:
+ return true;
+
+ default:
+ return false;
}
}
@@ -439,28 +438,27 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
// Traverse the basic block - bottom up
for (MachineBasicBlock::iterator MII = MBB->end(), E = MBB->begin();
MII != E;) {
- MachineInstr *MI = --MII;
- if (MI->isDebugValue()) {
+ MachineInstr &MI = *--MII;
+ if (MI.isDebugValue()) {
continue;
}
if ((nvjCount == 0) || (nvjCount > -1 && nvjCount <= nvjGenerated))
break;
- DEBUG(dbgs() << "Instr: "; MI->dump(); dbgs() << "\n");
+ DEBUG(dbgs() << "Instr: "; MI.dump(); dbgs() << "\n");
- if (!foundJump &&
- (MI->getOpcode() == Hexagon::J2_jumpt ||
- MI->getOpcode() == Hexagon::J2_jumpf ||
- MI->getOpcode() == Hexagon::J2_jumptnewpt ||
- MI->getOpcode() == Hexagon::J2_jumptnew ||
- MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
- MI->getOpcode() == Hexagon::J2_jumpfnew)) {
+ if (!foundJump && (MI.getOpcode() == Hexagon::J2_jumpt ||
+ MI.getOpcode() == Hexagon::J2_jumpf ||
+ MI.getOpcode() == Hexagon::J2_jumptnewpt ||
+ MI.getOpcode() == Hexagon::J2_jumptnew ||
+ MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
+ MI.getOpcode() == Hexagon::J2_jumpfnew)) {
// This is where you would insert your compare and
// instr that feeds compare
jmpPos = MII;
- jmpInstr = MI;
- predReg = MI->getOperand(0).getReg();
+ jmpInstr = &MI;
+ predReg = MI.getOperand(0).getReg();
afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
// If ifconverter had not messed up with the kill flags of the
@@ -489,13 +487,13 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
if (predLive)
break;
- if (!MI->getOperand(1).isMBB())
+ if (!MI.getOperand(1).isMBB())
continue;
- jmpTarget = MI->getOperand(1).getMBB();
+ jmpTarget = MI.getOperand(1).getMBB();
foundJump = true;
- if (MI->getOpcode() == Hexagon::J2_jumpf ||
- MI->getOpcode() == Hexagon::J2_jumpfnewpt ||
- MI->getOpcode() == Hexagon::J2_jumpfnew) {
+ if (MI.getOpcode() == Hexagon::J2_jumpf ||
+ MI.getOpcode() == Hexagon::J2_jumpfnewpt ||
+ MI.getOpcode() == Hexagon::J2_jumpfnew) {
invertPredicate = true;
}
continue;
@@ -504,41 +502,40 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
// No new value jump if there is a barrier. A barrier has to be in its
// own packet. A barrier has zero operands. We conservatively bail out
// here if we see any instruction with zero operands.
- if (foundJump && MI->getNumOperands() == 0)
+ if (foundJump && MI.getNumOperands() == 0)
break;
- if (foundJump &&
- !foundCompare &&
- MI->getOperand(0).isReg() &&
- MI->getOperand(0).getReg() == predReg) {
+ if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
+ MI.getOperand(0).getReg() == predReg) {
// Not all compares can be new value compare. Arch Spec: 7.6.1.1
if (isNewValueJumpCandidate(MI)) {
- assert((MI->getDesc().isCompare()) &&
+ assert(
+ (MI.getDesc().isCompare()) &&
"Only compare instruction can be collapsed into New Value Jump");
- isSecondOpReg = MI->getOperand(2).isReg();
+ isSecondOpReg = MI.getOperand(2).isReg();
if (!canCompareBeNewValueJump(QII, QRI, MII, predReg, isSecondOpReg,
afterRA, jmpPos, MF))
break;
- cmpInstr = MI;
+ cmpInstr = &MI;
cmpPos = MII;
foundCompare = true;
// We need cmpReg1 and cmpOp2(imm or reg) while building
// new value jump instruction.
- cmpReg1 = MI->getOperand(1).getReg();
- if (MI->getOperand(1).isKill())
+ cmpReg1 = MI.getOperand(1).getReg();
+ if (MI.getOperand(1).isKill())
MO1IsKill = true;
if (isSecondOpReg) {
- cmpOp2 = MI->getOperand(2).getReg();
- if (MI->getOperand(2).isKill())
+ cmpOp2 = MI.getOperand(2).getReg();
+ if (MI.getOperand(2).isKill())
MO2IsKill = true;
} else
- cmpOp2 = MI->getOperand(2).getImm();
+ cmpOp2 = MI.getOperand(2).getImm();
continue;
}
}
@@ -551,13 +548,12 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
bool foundFeeder = false;
MachineBasicBlock::iterator feederPos = MII;
- if (MI->getOperand(0).isReg() &&
- MI->getOperand(0).isDef() &&
- (MI->getOperand(0).getReg() == cmpReg1 ||
- (isSecondOpReg &&
- MI->getOperand(0).getReg() == (unsigned) cmpOp2))) {
+ if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
+ (MI.getOperand(0).getReg() == cmpReg1 ||
+ (isSecondOpReg &&
+ MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
- unsigned feederReg = MI->getOperand(0).getReg();
+ unsigned feederReg = MI.getOperand(0).getReg();
// First try to see if we can get the feeder from the first operand
// of the compare. If we can not, and if secondOpReg is true
@@ -606,15 +602,15 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
// the operands of the feeder.
bool updatedIsKill = false;
- for (unsigned i = 0; i < MI->getNumOperands(); i++) {
- MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0; i < MI.getNumOperands(); i++) {
+ MachineOperand &MO = MI.getOperand(i);
if (MO.isReg() && MO.isUse()) {
unsigned feederReg = MO.getReg();
for (MachineBasicBlock::iterator localII = feederPos,
end = jmpPos; localII != end; localII++) {
- MachineInstr *localMI = localII;
- for (unsigned j = 0; j < localMI->getNumOperands(); j++) {
- MachineOperand &localMO = localMI->getOperand(j);
+ MachineInstr &localMI = *localII;
+ for (unsigned j = 0; j < localMI.getNumOperands(); j++) {
+ MachineOperand &localMO = localMI.getOperand(j);
if (localMO.isReg() && localMO.isUse() &&
localMO.isKill() && feederReg == localMO.getReg()) {
// We found that there is kill of a use register
@@ -631,12 +627,12 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) {
if (updatedIsKill) break;
}
- MBB->splice(jmpPos, MI->getParent(), MI);
- MBB->splice(jmpPos, MI->getParent(), cmpInstr);
- DebugLoc dl = MI->getDebugLoc();
+ MBB->splice(jmpPos, MI.getParent(), MI);
+ MBB->splice(jmpPos, MI.getParent(), cmpInstr);
+ DebugLoc dl = MI.getDebugLoc();
MachineInstr *NewMI;
- assert((isNewValueJumpCandidate(cmpInstr)) &&
+ assert((isNewValueJumpCandidate(*cmpInstr)) &&
"This compare is not a New Value Jump candidate.");
unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2,
isSecondOpNewified,
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
index 6ddd3318f42..b064decc5c7 100644
--- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -132,15 +132,13 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
PeepholeDoubleRegsMap.clear();
// Traverse the basic block.
- for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
- ++MII) {
- MachineInstr *MI = MII;
+ for (MachineInstr &MI : *MBB) {
// Look for sign extends:
// %vreg170<def> = SXTW %vreg166
- if (!DisableOptSZExt && MI->getOpcode() == Hexagon::A2_sxtw) {
- assert (MI->getNumOperands() == 2);
- MachineOperand &Dst = MI->getOperand(0);
- MachineOperand &Src = MI->getOperand(1);
+ if (!DisableOptSZExt && MI.getOpcode() == Hexagon::A2_sxtw) {
+ assert(MI.getNumOperands() == 2);
+ MachineOperand &Dst = MI.getOperand(0);
+ MachineOperand &Src = MI.getOperand(1);
unsigned DstReg = Dst.getReg();
unsigned SrcReg = Src.getReg();
// Just handle virtual registers.
@@ -155,12 +153,11 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
// %vreg170:DoublRegs, %vreg169:IntRegs
- if (!DisableOptExtTo64 &&
- MI->getOpcode () == Hexagon::A4_combineir) {
- assert (MI->getNumOperands() == 3);
- MachineOperand &Dst = MI->getOperand(0);
- MachineOperand &Src1 = MI->getOperand(1);
- MachineOperand &Src2 = MI->getOperand(2);
+ if (!DisableOptExtTo64 && MI.getOpcode() == Hexagon::A4_combineir) {
+ assert(MI.getNumOperands() == 3);
+ MachineOperand &Dst = MI.getOperand(0);
+ MachineOperand &Src1 = MI.getOperand(1);
+ MachineOperand &Src2 = MI.getOperand(2);
if (Src1.getImm() != 0)
continue;
unsigned DstReg = Dst.getReg();
@@ -173,11 +170,11 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
// and convert into
// %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
- if (MI->getOpcode() == Hexagon::S2_lsr_i_p) {
- assert(MI->getNumOperands() == 3);
- MachineOperand &Dst = MI->getOperand(0);
- MachineOperand &Src1 = MI->getOperand(1);
- MachineOperand &Src2 = MI->getOperand(2);
+ if (MI.getOpcode() == Hexagon::S2_lsr_i_p) {
+ assert(MI.getNumOperands() == 3);
+ MachineOperand &Dst = MI.getOperand(0);
+ MachineOperand &Src1 = MI.getOperand(1);
+ MachineOperand &Src2 = MI.getOperand(2);
if (Src2.getImm() != 32)
continue;
unsigned DstReg = Dst.getReg();
@@ -187,11 +184,10 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
}
// Look for P=NOT(P).
- if (!DisablePNotP &&
- (MI->getOpcode() == Hexagon::C2_not)) {
- assert (MI->getNumOperands() == 2);
- MachineOperand &Dst = MI->getOperand(0);
- MachineOperand &Src = MI->getOperand(1);
+ if (!DisablePNotP && MI.getOpcode() == Hexagon::C2_not) {
+ assert(MI.getNumOperands() == 2);
+ MachineOperand &Dst = MI.getOperand(0);
+ MachineOperand &Src = MI.getOperand(1);
unsigned DstReg = Dst.getReg();
unsigned SrcReg = Src.getReg();
// Just handle virtual registers.
@@ -206,10 +202,10 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// Look for copy:
// %vreg176<def> = COPY %vreg170:subreg_loreg
- if (!DisableOptSZExt && MI->isCopy()) {
- assert (MI->getNumOperands() == 2);
- MachineOperand &Dst = MI->getOperand(0);
- MachineOperand &Src = MI->getOperand(1);
+ if (!DisableOptSZExt && MI.isCopy()) {
+ assert(MI.getNumOperands() == 2);
+ MachineOperand &Dst = MI.getOperand(0);
+ MachineOperand &Src = MI.getOperand(1);
// Make sure we are copying the lower 32 bits.
if (Src.getSubReg() != Hexagon::subreg_loreg)
@@ -222,22 +218,18 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// Try to find in the map.
if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
// Change the 1st operand.
- MI->RemoveOperand(1);
- MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
+ MI.RemoveOperand(1);
+ MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
} else {
DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
PeepholeDoubleRegsMap.find(SrcReg);
if (DI != PeepholeDoubleRegsMap.end()) {
std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
- MI->RemoveOperand(1);
- MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
- false /*isDef*/,
- false /*isImp*/,
- false /*isKill*/,
- false /*isDead*/,
- false /*isUndef*/,
- false /*isEarlyClobber*/,
- PeepholeSrc.second));
+ MI.RemoveOperand(1);
+ MI.addOperand(MachineOperand::CreateReg(
+ PeepholeSrc.first, false /*isDef*/, false /*isImp*/,
+ false /*isKill*/, false /*isDead*/, false /*isUndef*/,
+ false /*isEarlyClobber*/, PeepholeSrc.second));
}
}
}
@@ -246,8 +238,8 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// Look for Predicated instructions.
if (!DisablePNotP) {
bool Done = false;
- if (QII->isPredicated(*MI)) {
- MachineOperand &Op0 = MI->getOperand(0);
+ if (QII->isPredicated(MI)) {
+ MachineOperand &Op0 = MI.getOperand(0);
unsigned Reg0 = Op0.getReg();
const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
if (RC0->getID() == Hexagon::PredRegsRegClassID) {
@@ -257,9 +249,9 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
// Try to find in the map.
if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
// Change the 1st operand and, flip the opcode.
- MI->getOperand(0).setReg(PeepholeSrc);
- int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
- MI->setDesc(QII->get(NewOp));
+ MI.getOperand(0).setReg(PeepholeSrc);
+ int NewOp = QII->getInvertedPredicatedOpcode(MI.getOpcode());
+ MI.setDesc(QII->get(NewOp));
Done = true;
}
}
@@ -268,7 +260,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
if (!Done) {
// Handle special instructions.
- unsigned Op = MI->getOpcode();
+ unsigned Op = MI.getOpcode();
unsigned NewOp = 0;
unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
@@ -285,15 +277,15 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
break;
}
if (NewOp) {
- unsigned PSrc = MI->getOperand(PR).getReg();
+ unsigned PSrc = MI.getOperand(PR).getReg();
if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
- MI->getOperand(PR).setReg(POrig);
- MI->setDesc(QII->get(NewOp));
+ MI.getOperand(PR).setReg(POrig);
+ MI.setDesc(QII->get(NewOp));
// Swap operands S1 and S2.
- MachineOperand Op1 = MI->getOperand(S1);
- MachineOperand Op2 = MI->getOperand(S2);
- ChangeOpInto(MI->getOperand(S1), Op2);
- ChangeOpInto(MI->getOperand(S2), Op1);
+ MachineOperand Op1 = MI.getOperand(S1);
+ MachineOperand Op2 = MI.getOperand(S2);
+ ChangeOpInto(MI.getOperand(S1), Op2);
+ ChangeOpInto(MI.getOperand(S2), Op1);
}
} // if (NewOp)
} // if (!Done)
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
index e13e2d2a263..5a94cce4ce5 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
@@ -86,55 +86,56 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
MachineBasicBlock::iterator MII = MBB->begin();
MachineBasicBlock::iterator MIE = MBB->end ();
while (MII != MIE) {
- MachineInstr *MI = MII;
- int Opc = MI->getOpcode();
+ MachineInstr &MI = *MII;
+ int Opc = MI.getOpcode();
if (Opc == Hexagon::CONST32_Int_Real &&
- MI->getOperand(1).isBlockAddress()) {
- int DestReg = MI->getOperand(0).getReg();
- MachineOperand &Symbol = MI->getOperand (1);
-
- BuildMI (*MBB, MII, MI->getDebugLoc(),
- TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
- BuildMI (*MBB, MII, MI->getDebugLoc(),
- TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
+ MI.getOperand(1).isBlockAddress()) {
+ int DestReg = MI.getOperand(0).getReg();
+ MachineOperand &Symbol = MI.getOperand(1);
+
+ BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::LO), DestReg)
+ .addOperand(Symbol);
+ BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::HI), DestReg)
+ .addOperand(Symbol);
// MBB->erase returns the iterator to the next instruction, which is the
// one we want to process next
- MII = MBB->erase (MI);
+ MII = MBB->erase(&MI);
continue;
}
else if (Opc == Hexagon::CONST32_Int_Real ||
Opc == Hexagon::CONST32_Float_Real) {
- int DestReg = MI->getOperand(0).getReg();
+ int DestReg = MI.getOperand(0).getReg();
// We have to convert an FP immediate into its corresponding integer
// representation
int64_t ImmValue;
if (Opc == Hexagon::CONST32_Float_Real) {
- APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
+ APFloat Val = MI.getOperand(1).getFPImm()->getValueAPF();
ImmValue = *Val.bitcastToAPInt().getRawData();
}
else
- ImmValue = MI->getOperand(1).getImm();
+ ImmValue = MI.getOperand(1).getImm();
- BuildMI(*MBB, MII, MI->getDebugLoc(),
- TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue);
- MII = MBB->erase (MI);
+ BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
+ DestReg)
+ .addImm(ImmValue);
+ MII = MBB->erase(&MI);
continue;
}
else if (Opc == Hexagon::CONST64_Int_Real ||
Opc == Hexagon::CONST64_Float_Real) {
- int DestReg = MI->getOperand(0).getReg();
+ int DestReg = MI.getOperand(0).getReg();
// We have to convert an FP immediate into its corresponding integer
// representation
int64_t ImmValue;
if (Opc == Hexagon::CONST64_Float_Real) {
- APFloat Val = MI->getOperand(1).getFPImm()->getValueAPF();
+ APFloat Val = MI.getOperand(1).getFPImm()->getValueAPF();
ImmValue = *Val.bitcastToAPInt().getRawData();
}
else
- ImmValue = MI->getOperand(1).getImm();
+ ImmValue = MI.getOperand(1).getImm();
unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
@@ -142,11 +143,13 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
int32_t LowWord = (ImmValue & 0xFFFFFFFF);
int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
- BuildMI(*MBB, MII, MI->getDebugLoc(),
- TII->get(Hexagon::A2_tfrsi), DestLo).addImm(LowWord);
- BuildMI (*MBB, MII, MI->getDebugLoc(),
- TII->get(Hexagon::A2_tfrsi), DestHi).addImm(HighWord);
- MII = MBB->erase (MI);
+ BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
+ DestLo)
+ .addImm(LowWord);
+ BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::A2_tfrsi),
+ DestHi)
+ .addImm(HighWord);
+ MII = MBB->erase(&MI);
continue;
}
++MII;
diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 7051ee32abf..033c02154db 100644
--- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -111,13 +111,14 @@ HexagonPacketizerList::HexagonPacketizerList(MachineFunction &MF,
}
// Check if FirstI modifies a register that SecondI reads.
-static bool hasWriteToReadDep(const MachineInstr *FirstI,
- const MachineInstr *SecondI, const TargetRegisterInfo *TRI) {
- for (auto &MO : FirstI->operands()) {
+static bool hasWriteToReadDep(const MachineInstr &FirstI,
+ const MachineInstr &SecondI,
+ const TargetRegisterInfo *TRI) {
+ for (auto &MO : FirstI.operands()) {
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO.getReg();
- if (SecondI->readsRegister(R, TRI))
+ if (SecondI.readsRegister(R, TRI))
return true;
}
return false;
@@ -148,7 +149,7 @@ static MachineBasicBlock::iterator moveInstrOut(MachineInstr *MI,
B.splice(InsertPt, &B, MI);
// Get the size of the bundle without asserting.
- MachineBasicBlock::const_instr_iterator I(BundleIt);
+ MachineBasicBlock::const_instr_iterator I = BundleIt.getInstrIterator();
MachineBasicBlock::const_instr_iterator E = B.instr_end();
unsigned Size = 0;
for (++I; I != E && I->isBundledWithPred(); ++I)
@@ -367,7 +368,7 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr *MI,
const TargetRegisterClass *RC) {
if (!HII->isV60VectorInstruction(MI))
return false;
- if (!HII->isV60VectorInstruction(MII))
+ if (!HII->isV60VectorInstruction(&*MII))
return false;
// Already a dot new instruction.
@@ -385,11 +386,14 @@ bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr *MI,
DEBUG(dbgs() << "Can we DOT Cur Vector MI\n";
MI->dump();
dbgs() << "in packet\n";);
- MachineInstr *MJ = MII;
- DEBUG(dbgs() << "Checking CUR against "; MJ->dump(););
+ MachineInstr &MJ = *MII;
+ DEBUG({
+ dbgs() << "Checking CUR against ";
+ MJ.dump();
+ });
unsigned DestReg = MI->getOperand(0).getReg();
bool FoundMatch = false;
- for (auto &MO : MJ->operands())
+ for (auto &MO : MJ.operands())
if (MO.isReg() && MO.getReg() == DestReg)
FoundMatch = true;
if (!FoundMatch)
@@ -1018,7 +1022,7 @@ void HexagonPacketizerList::unpacketizeSoloInstrs(MachineFunction &MF) {
// after the bundle (to preserve the bundle semantics).
bool InsertBeforeBundle;
if (MI->isInlineAsm())
- InsertBeforeBundle = !hasWriteToReadDep(MI, BundleIt, HRI);
+ InsertBeforeBundle = !hasWriteToReadDep(*MI, *BundleIt, HRI);
else if (MI->isDebugValue())
InsertBeforeBundle = true;
else
@@ -1160,12 +1164,12 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
// If an instruction feeds new value jump, glue it.
MachineBasicBlock::iterator NextMII = I;
++NextMII;
- if (NextMII != I->getParent()->end() && HII->isNewValueJump(NextMII)) {
- MachineInstr *NextMI = NextMII;
+ if (NextMII != I->getParent()->end() && HII->isNewValueJump(&*NextMII)) {
+ MachineInstr &NextMI = *NextMII;
bool secondRegMatch = false;
- const MachineOperand &NOp0 = NextMI->getOperand(0);
- const MachineOperand &NOp1 = NextMI->getOperand(1);
+ const MachineOperand &NOp0 = NextMI.getOperand(0);
+ const MachineOperand &NOp1 = NextMI.getOperand(1);
if (NOp1.isReg() && I->getOperand(0).getReg() == NOp1.getReg())
secondRegMatch = true;
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