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-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp2
-rw-r--r--llvm/test/CodeGen/AArch64/arm64-fp128.ll22
2 files changed, 23 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index bb67aa3df72..478bebe0926 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -216,7 +216,7 @@ void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
case ISD::SETUEQ:
LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
(VT == MVT::f64) ? RTLIB::UO_F64 :
- (VT == MVT::f128) ? RTLIB::UO_F64 : RTLIB::UO_PPCF128;
+ (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128;
LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
(VT == MVT::f64) ? RTLIB::OEQ_F64 :
(VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128;
diff --git a/llvm/test/CodeGen/AArch64/arm64-fp128.ll b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
index 78ba9a01cbe..164351ec71d 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fp128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fp128.ll
@@ -156,6 +156,28 @@ define i1 @test_setcc2() {
; CHECK: ret
}
+define i1 @test_setcc3() {
+; CHECK-LABEL: test_setcc3:
+
+ %lhs = load fp128, fp128* @lhs, align 16
+ %rhs = load fp128, fp128* @rhs, align 16
+; CHECK: ldr q0, [{{x[0-9]+}}, :lo12:lhs]
+; CHECK: ldr q1, [{{x[0-9]+}}, :lo12:rhs]
+
+ %val = fcmp ueq fp128 %lhs, %rhs
+; CHECK: bl __eqtf2
+; CHECK: cmp w0, #0
+; CHECK: cset w19, eq
+; CHECK: bl __unordtf2
+; CHECK: cmp w0, #0
+; CHECK: cset w8, ne
+; CHECK: orr w0, w8, w19
+
+ ret i1 %val
+; CHECK: ret
+}
+
+
define i32 @test_br_cc() {
; CHECK-LABEL: test_br_cc:
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